Byte alignment for serial data receiver

• US 7,046,174 B1
• Filed: 06/07/2005
• Issued: 05/16/2006
• Est. Priority Date: 06/03/2003
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Lam, John, Patel, Rakesh, Venkata, Ramanand, Lee, Chong H., Chan, Vinson, Lui, Henry Y., Kabani, Malik
• Primary Examiner(s): Barnie, Rexford
• Assistant Examiner(s): LAUTURE, JOSEPH J
• Application Number:
  US11/147,757
• Time in Patent Office: 343 Days
• Field of Search: None
• US Class Current: 341/101
• CPC Class Codes: H03K 5/135 by the use of time reference signals, e.g. clock signals
• CPC Class Codes: H03M 9/00 Parallel/series conversion or vice versa digital stores in which the information is moved stepwise per se G11C19/00
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence

Abstract

A serial data interface for a programmable logic device includes a receiver that deserializes a plurality of channels of received serial data using a recovered clock signal or a phase-aligned received clock signal. Byte boundaries are initially assigned, perhaps arbitrarily, and the deserialized signal is sent to the programmable logic core of the programmable logic device. Programmable logic in the core monitors the byte boundaries on each channel based on the criteria, including any user-defined parameters, programmed into the logic. If a boundary misalignment is detected, a signal is send from the core to bit-slipping circuitry on that channel of the interface to adjust the boundary. The signal could instruct the bit-slipping circuitry to adjust the boundary by the number of bits needed to correct the alignment. Alternatively, the bit-slipping circuitry could operate iteratively, adjusting the boundary by one bit, each cycle, until the signal stops indicating misalignment.

Claims

1. A method of aligning a boundary between bytes of a deserialized serial data signal, said method comprising:

receiving a serial data signal;

deserializing said serial data signal, including inserting an initial candidate byte boundary between selected bits of said deserialized data signal;

transmitting said deserialized data signal;

processing said deserialized signal with said initial candidate byte boundary to validate said initial candidate byte boundary; and

generating a byte alignment error when said candidate boundary is determined to be invalid.

2. The method of claim 1 further comprising:

assigning based on said error signal an alternate candidate byte boundary between different selected bits of said deserialized data signal;

retransmitting said deserialized data signal with said alternate candidate byte boundary; and

reprocessing said retransmitted deserialized data signal with said alternate candidate byte boundary to validate said alternate candidate byte boundary.

3. The method of claim 2 wherein:

said error signal indicates a number of bits of discrepancy in said byte boundary; and

said assigning an alternate candidate byte boundary comprises moving said byte boundary by said number of bits of discrepancy.

4. The method of claim 2 wherein:

said assigning an alternate candidate byte boundary comprises moving said byte boundary by one bit; and

said sending, said assigning, said retransmitting and said reprocessing occur iteratively until said reprocessing determines that said alternate candidate byte boundary is correct.

5. A programmable logic device comprising:

a serial data interface adapted to receive and deserialize a serial data signal, said serial data interface comprising bit-slipping circuitry adapted to a insert a byte boundary between bits of said deserialized data signal, said bit-slipping circuitry being responsive to a bit-slipping control signal from another portion of said programmable logic device.

6. The programmable logic device of claim 5 wherein said bit-slipping circuitry comprises bit-handling circuitry and control circuitry that controls said bit-handling circuitry responsive to said bit-slipping control signal.

7. The programmable logic device of claim 6 wherein:

each byte includes a first number of bits; and

said bit-handling circuitry comprises;

at least one shift register for receiving said serial data, and having capacity to hold a second number of bits greater than said first number of bits, and further having a number of parallel outputs equal to said second number of bits, and

selection circuitry having a number of selection inputs equal to said number of parallel outputs of said at least one shift register, and having a number of selection outputs equal to said first number of bits, said selection inputs being connected to said parallel outputs of said at least one shift register;

wherein;

said control circuitry controls which of said selection inputs is connected to said selection outputs.

8. The programmable logic device of claim 7 wherein said selection circuitry is a barrel shifter.

9. The programmable logic device of claim 7 wherein said second number of bits is twice said first number of bits.

10. The programmable logic device of claim 9 wherein said at least one shift register comprises two shift registers chained serially, each of said shift registers having capacity to hold said first number of bits.

11. A digital processing system comprising:

processing circuitry;

a memory coupled to said processing circuitry; and

a programmable logic device as defined in claim 5 coupled to the processing circuitry and the memory.

12. A printed circuit board on which is mounted a programmable logic device as defined in claim 5.

13. The printed circuit board defined in claim 12 further comprising:

memory circuitry mounted on the printed circuit board and coupled to the programmable logic device.

14. The printed circuit board defined in claim 13 further comprising:

processing circuitry mounted on the printed circuit board and coupled to the memory circuitry.

15. A serial data interface for use with a programmable logic device, said serial data interface being adapted to receive and deserialize a serial data signal, said serial data interface comprising:

bit-slipping circuitry adapted to insert a byte boundary between bits of said deserialized serial data signal, said bit-slipping circuitry being responsive to a bit-slipping control signal from another portion of said programmable logic device.

16. The serial data interface of claim 15 wherein said bit-slipping circuitry comprises bit-handling circuitry and control circuitry that controls said bit-handling circuitry responsive to said bit-slipping control signal.

17. The serial data interface of claim 16 wherein:

each byte includes a first number of bits; and

said bit-handling circuitry comprises;

at least one shift register for receiving said serial data, and having capacity to hold a second number of bits greater than said first number of bits, and further having a number of parallel outputs equal to said second number of bits, and

selection circuitry having a number of selection inputs equal to said number of parallel outputs of said at least one shift register, and having a number of selection outputs equal to said first number of bits, said selection inputs being connected to said parallel outputs of said at least one shift register;

wherein;

said control circuitry controls which of said selection inputs is connected to said selection outputs.

18. The serial data interface of claim 17 wherein said selection circuitry is a barrel shifter.

19. The serial data interface of claim 17 wherein said second number of bits is twice said first number of bits.

20. The serial data interface of claim 19 wherein said at least one shift register comprises two shift registers chained serially, each of said shift registers having capacity to hold said first number of bits.

21. A programmable logic device comprising the serial data interface of claim 15.

22. A digital processing system comprising:

processing circuitry;

a memory coupled to said processing circuitry; and

a programmable logic device as defined in claim 21 coupled to the processing circuitry and the memory.

23. A printed circuit board on which is mounted a programmable logic device as defined in claim 21.

24. The printed circuit board defined in claim 23 further comprising:

memory circuitry mounted on the printed circuit board and coupled to the programmable logic device.

25. The printed circuit board defined in claim 24 further comprising:

processing circuitry mounted on the printed circuit board and coupled to the memory circuitry.