Byte alignment for serial data receiver
First Claim
1. A method of aligning a boundary between bytes of a deserialized serial data signal, said method comprising:
- receiving a serial data signal;
deserializing said serial data signal, including inserting an initial candidate byte boundary between selected bits of said deserialized data signal;
transmitting said deserialized data signal;
processing said deserialized signal with said initial candidate byte boundary to validate said initial candidate byte boundary; and
generating a byte alignment error when said candidate boundary is determined to be invalid.
0 Assignments
0 Petitions
Accused Products
Abstract
A serial data interface for a programmable logic device includes a receiver that deserializes a plurality of channels of received serial data using a recovered clock signal or a phase-aligned received clock signal. Byte boundaries are initially assigned, perhaps arbitrarily, and the deserialized signal is sent to the programmable logic core of the programmable logic device. Programmable logic in the core monitors the byte boundaries on each channel based on the criteria, including any user-defined parameters, programmed into the logic. If a boundary misalignment is detected, a signal is send from the core to bit-slipping circuitry on that channel of the interface to adjust the boundary. The signal could instruct the bit-slipping circuitry to adjust the boundary by the number of bits needed to correct the alignment. Alternatively, the bit-slipping circuitry could operate iteratively, adjusting the boundary by one bit, each cycle, until the signal stops indicating misalignment.
-
Citations
25 Claims
-
1. A method of aligning a boundary between bytes of a deserialized serial data signal, said method comprising:
-
receiving a serial data signal; deserializing said serial data signal, including inserting an initial candidate byte boundary between selected bits of said deserialized data signal; transmitting said deserialized data signal; processing said deserialized signal with said initial candidate byte boundary to validate said initial candidate byte boundary; and generating a byte alignment error when said candidate boundary is determined to be invalid. - View Dependent Claims (2, 3, 4)
-
-
5. A programmable logic device comprising:
a serial data interface adapted to receive and deserialize a serial data signal, said serial data interface comprising bit-slipping circuitry adapted to a insert a byte boundary between bits of said deserialized data signal, said bit-slipping circuitry being responsive to a bit-slipping control signal from another portion of said programmable logic device. - View Dependent Claims (6, 7, 8, 9, 10, 11, 12, 13, 14)
-
15. A serial data interface for use with a programmable logic device, said serial data interface being adapted to receive and deserialize a serial data signal, said serial data interface comprising:
bit-slipping circuitry adapted to insert a byte boundary between bits of said deserialized serial data signal, said bit-slipping circuitry being responsive to a bit-slipping control signal from another portion of said programmable logic device. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
Specification