Semiconductor memory device with improved data retention characteristics

• US 7,046,543 B2
• Filed: 08/23/2004
• Issued: 05/16/2006
• Est. Priority Date: 05/21/2001
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Arimoto, Kazutami, Shimano, Hiroki
• Primary Examiner(s): Yoha, Connie C.
• Application Number:
  US10/922,936
• Publication Number:
  US 20050018471A1
• Time in Patent Office: 631 Days
• Field of Search: 365/149, 365/230.06, 365/230.03, 365/189.09
• US Class Current: 365/149
• CPC Class Codes: G11C 11/4085 Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 2211/4013 Memory devices with multiple cells per bit, e.g. twin-cells
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/03 Making the capacitor or connections thereto
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/48 Data lines or contacts therefor

Abstract

Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charge form. By forming the capacitors of the memory cells into a planar capacitor configuration, a step due to the capacitors is removed. Thus, a dynamic semiconductor memory device can be formed through CMOS process, and a dynamic semiconductor memory device suitable for merging with logic is achieved. Data of 1 bit is stored by two memory cells, and data can be reliably stored even if the capacitance value of the memory cell is reduced due to the planar type capacitor.

Claims

1. A semiconductor memory device, comprising:

memory cells arranged in rows and columns, each memory cell including a capacitor including a cell plate electrode for receiving a reference voltage, and a storage electrode arranged facing to the cell plate node, for accumulating electric charges corresponding to storage data;

a plurality of word lines arranged corresponding to the rows of memory cells and each connecting to the memory cells on a corresponding row, the word lines comprising an interconnection line formed in a same interconnection layer as the cell plate electrodes, the cell plate electrodes and the word lines being arranged in pairs;

word line selecting circuitry for selecting a word line arranged corresponding to an addressed row in accordance with an address signal; and

cell plate voltage control circuitry for changing a voltage of a cell plate electrode provided for a selected word line on the addressed row from a predetermined reference voltage level after the word line is selected, and returning the cell plate electrode voltage to the reference voltage level when the selected word line is deactivated, and maintaining the voltage level of the cell plate electrode for a non-selected word line other than the selected word line at the reference voltage level.

2. A semiconductor memory device, comprising:

a plurality of memory cells, arranged in rows and columns, each including a capacitor comprising a cell plate electrode for receiving a reference voltage and a storage electrode for accumulating electric charges corresponding to storage data;

a plurality of word lines, arranged corresponding to the rows of memory cells, each connecting to the memory cells on a corresponding row and comprising an interconnection line formed in a lower first interconnection layer different from the cell plate electrode, and said cell plate electrode comprising an interconnection line of a second interconnection layer above the first interconnection layer; and

a plurality of bit lines, arranged corresponding to the columns of memory cells, each connecting to the memory cells on a corresponding column, and formed above the word lines and the cell plate electrode, the memory cells being arranged such that the memory cells are arranged staggered by one column in a column direction with two memory cells being a unit, and the unit of the memory cells is arranged in one of adjacent columns in a row direction, the bit lines forming a pair with a bit line of another pair interposed in between, the capacitors of the memory cells being simultaneously connected to the bit lines in the pair, and 1-bit data being stored in the memory cells having the capacitors connected to the bit lines.

3. The semiconductor memory device according to claim 2, wherein said first interconnection layer is a polysilicon interconnection layer containing an impurity implanted to a semiconductor substrate region thereunder for adjusting a threshold voltage and formed through dual polysilicon gate process, and said second interconnection layer is made of an impurity implanted polysilicon interconnection layer having an impurity implanted independently of the impurity implanted to said semiconductor substrate region.

4. The semiconductor memory device according to claim 2, wherein said cell plate electrode is arranged, in a meshed shape, extending over an area where the memory cells are arranged.

5. The semiconductor memory device according to claim 4, wherein said cell plate electrode have a contact hole formed in an area provided in an area, having the memory cells arranged therein, for driving the selected word line at a high speed.

6. The semiconductor memory device according to claim 2, wherein the word lines and the cell plate electrode have side wall insulating films formed on their respective side walls, and said side wall insulating films cover an impurity region connected to the storage node of said capacitor.