GPS RF front end IC with frequency plan for improved integrability

• US 7,047,023 B1
• Filed: 12/03/2001
• Issued: 05/16/2006
• Est. Priority Date: 12/01/2000
• Status: Expired due to Term

• Current Assignee: CSR Technology Incorporated (Qualcomm, Inc.)
• Original Assignee: SIRF Technology Incorporated (Qualcomm, Inc.)
• Inventors: Tso, Robert
• Primary Examiner(s): Kuntz, Curtis
• Assistant Examiner(s): Sams, Matthew C
• Application Number:
  US10/011,546
• Time in Patent Office: 1,625 Days
• Field of Search: 340/426.19, 340/539.13, 34235706-35715, 701213-216, 455130-355, 455/456.1, 455/456.6, 455255-265
• US Class Current: 455/456.6
• CPC Class Codes: G01S 19/36 relating to the receiver frond end
• CPC Class Codes: H04B 1/0475 with means for limiting noise, interference or distortion H04B1/0483 takes precedence

Abstract

A GPS RF Front End IC using a single conversion stage, which is immune from self jamming from clock signal harmonics generated internally or from dominant clock signal harmonics generated externally by the subsequent baseband GPS processor which uses a clock of 48•fo for GPS processing. The improved frequency plan reduces the problems of interference when the integration of the RF and Baseband functions is required in the form of a single-chip, or as 2 individual chips on a common substrate.

Claims

1. A GPS RF front end integrated circuit, comprising:

input means for accepting a 13 MHz reference signal;

a voltage controlled oscillator (VCO having an input, the VCO providing a Local Oscillator (LO) signal of approximately 1536 fo,

a divide-by-4 prescaler, having an input coupled to the VCO output;

a Programmable Modulus (PM) divider, having an input;

an accumulator, having an addend input and an output sum, the accumulator being coupled to the input of the PM divider, comprising an overflow bit which controls the selectable divider, wherein the overflow bit is used to provide a time averaged divide ratio of 30.21875;

a first register coupled to the addend input of the accumulator;

a second register coupled to the output sum of the accumulator;

a first mixer and a second mixer for providing an image reject mixer function;

a first IF filter and a second IF filter, each having a center frequency of 4 fo and each having high attenuation near dc;

an IF combiner circuit to effect image rejection by phase shifting and summation;

a divide-by-8 counter to synthesize a CLKGPS signal;

a divide-by-3 counter to synthesize a CLKACQ signal;

a linear AGC function; and

an A/D converter which provides a sampled, digital representation of the IF signal.

2. The GPS RF front end circuit of claim 1, wherein the selectable divider can be selected to perform a divide-by-30 function or a divide-by-31 function.

3. The GPS RF front end circuit of claim 2, wherein the accumulator comprises at least 5 bits.

4. The GPS RF front end of claim 3, wherein the overflow bit controls the selection of the divide-by-30 function or the divide-by-31 function of the selectable divider.

5. The GPS RF front end of claim 4, wherein the CLKGPS signal has a frequency at a value of 48 fo.

6. The GPS RF front end of claim 5, wherein the CLKACQ signal has a frequency at a value of 16 fo.