Method and VLSI circuits allowing to change dynamically the logical behavior

• US 7,047,166 B2
• Filed: 06/06/2001
• Issued: 05/16/2006
• Est. Priority Date: 02/27/2001
• Status: Expired due to Fees

• Current Assignee: Ioan Dancea
• Original Assignee: Ioan Dancea
• Inventors: Dancea, Ioan
• Primary Examiner(s): FERRIS III, FRED O
• Application Number:
  US09/874,027
• Publication Number:
  US 20020173938A1
• Time in Patent Office: 1,805 Days
• Field of Search: 703/2, 703/13, 703/14, 703/15, 716/12, 716/17, 708/232, 708/603, 326 38- 41, 327/144, 327/145
• US Class Current: 703/2
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/343 Logical level
• CPC Class Codes: H03G 5/005 of digital signals

Abstract

A method, named the product terms method that allows to implement and/or to change dynamically the logical behavior of any combinational or synchronous sequential circuits has been presented. The method uses for every product term of logical equations, expressed as a sum-of-product, three memory words: mask word, product word and function word. The words of all product terms are ranged in a table, which characterize the logical behavior of the circuit.

The invention provides the hardware structure of several new types of VSLI circuits, having re-configurable logic behaviors. A first embodiment implements any type of multiple output combinational circuit, a second embodiment implements any synchronous sequential circuit with only clock input and, a third embodiment implements any synchronous sequential circuit s with data inputs and clock input.

An expert system capable to generate the tables used for the product terms method by interpreting and analysing the logical equations either supplied by the user or found in a database is also provided.

Claims

1. A dynamically reconfigurable VLSI device for implementing in hardware any multiple outputs combinational target circuit having the output functions expressed in logical sum-of-product equations with a maximum of m inputs, a maximum of r outputs and a maximum of n product terms p(k), comprising:

a register with m bits for storing the input variables;

n cells, a cell C(k) for determining the logical value of a product term p(k) of said equations for given inputs;

a block of r OR gates, each one with n inputs, associated with said cells C(k) for receiving the logical value of product terms p(k) and outputting the r bits of output functions;

wherein said cell C(k) comprises;

a storage area for storing the information that characterizes a product term, named mask word, product word and function word;

first logic level means for receiving said m inputs and said mask word to produce a first intermediate result, which identify the input variables that form a product term;

second logic level means for comparing the said product term with said first intermediate result to produce a second intermediate result concerning a product term;

third logic level means for receiving said second intermediate result to produce the logical value of the product term; and

forth logic level means for transferring said function word to r outputs, according to said logical value of said product term p(k), and subsequently to be OR-ed with function words of other product terms.

2. A dynamically reconfigurable VLSI device as in claim 1, wherein said storage area of a cell C(k) comprises two m-bit registers and one r-bit register.

3. A dynamically reconfigurable VLSI device as in claim 1, wherein said first logic level of a cell C(k) comprises m*(2-bit) AND gates, each one for receiving a respective bit of said m input variables and of said mask word to produce said first intermediate result.

4. A dynamically reconfigurable VLSI device as in claim 1, wherein said second logic level of a cell C(k) comprises m*(2-bit) XNOR gates, each one for receiving a respective bit of said first intermediate result and of said product word to produce a bit of said second intermediate result.

5. A dynamically reconfigurable VLSI device as in claim 1, wherein said third logic level of a cell C(k) comprises one m-bit AND gate to produce a logical value which is the value of the product term.

6. A dynamically reconfigurable VLSI device as in claim 1, wherein said forth logic level of a cell C(k) comprises m*(2-bit) AND gates for transferring said function word to outputs, considering the logical value of said product term p(k).

7. A dynamically reconfigurable VLSI device for implementing in hardware a target synchronous sequential circuit with maximum 2^s states, clock input only and outputs taken from the state register, wherein the multiple outputs combinational circuit which establish the next state defined by sum-of-product logical equations is implemented according to claim 1, with maximum s inputs, maximum s outputs and maximum n product terms p(k) and wherein the input register is a state register with s bits;

and further comprising;

a feedback connection to establish the next state.

8. A dynamically reconfigurable VLSI device for implementing in hardware a target synchronous sequential circuit with maximum 2^s states, m data inputs, clock input and r outputs, wherein two multiple outputs combinational circuits are implemented according to claim 1, the first combinational circuit defined by the next state sum-of-product logical equations with maximum (m+s) inputs, maximum s outputs and maximum n1 product terms p(k) and the second combinational circuit defined by the output sum-of-product logical equations, with maximum s inputs, maximum r outputs, and maximum n2 product terms p(k);

and further comprising;

a state register with s bits, wherein said state register is the input register of the second combinational circuit;

a feedback connection to establish the next state.

12. A method for implementing target circuits selected from multiple-output combinational circuits and from synchronous sequential circuits, having their behavior described by groups of logical sum-of-product equations, wherein each said group of logical sum-of-product equations is implemented in a dynamically reconfigurable VLSI device, as in claim 1 or 9, the method comprising the steps of:

inputting a request to reconfigure said VLSI device to said target circuit;

identifying the VLSI device to be configured, considering its internal structure, of type cell C(k) or of type modified cell C(k);

generating memory words uniquely defining each product term p(k) of said sum-of-products logical equations; and

implementing the target circuit by storing said memory words into a corresponding registers of type cell C(k) or of type modified cell C(k).

9. A dynamically reconfigurable VLSI device for implementing in hardware any multiple-output combinational target circuit defined by a group of logical sum-of-product equations, with maximum m inputs, maximum r outputs and a maximum of q product terms in each equation, having a register with m bits for storing the input variables and for each single sum-of-products logical equation, considered as an independent equation, further comprising:

q modified cells, a modified cell C(k) for determining the logical value of a product term p(k) of said independent equation, for given inputs;

a single OR gate associated with said q modified cell C(k) for receiving the logical value of product terms p(k) to provide a single output for said independent equation;

wherein said modified cell C(k) comprises;

a storage area formed by two m-bit registers for storing the information that characterizes a product term, named mask word and product word;

first logic level that comprises m*(2-bit) AND gates, each one for receiving a respective bit of said inputs and of said mask word to produce a respective bit of first intermediate result, which identify the input variables that form a product term;

second logic level that comprises m*(2-bit) XNOR gates, each one for receiving a respective bit of said product word and said first intermediate result to produce a second intermediate result concerning a product term; and

third logic level that comprises one m-bit AND gate for receiving the m bits of said second intermediate result to produce a logical value which is the value of the product term.

10. A dynamically reconfigurable VLSI device for implementing in hardware a target synchronous sequential circuit with maximum 2^s states, clock input only and outputs taken from the state register, wherein the multiple outputs combinational circuit which establish the next state defined by sum-of-product logical equations is implemented according to claim 9, with maximum s inputs, maximum s outputs and maximum q product terms p(k) in each said equation and wherein the input register is a state register with s bits;

and further comprising;

a feedback connection to establish the next state.

11. A dynamically reconfigurable VLSI device for implementing in hardware a target synchronous sequential circuit with maximum 2^s states, m data inputs, clock input and r outputs, wherein two multiple outputs combinational circuits are implemented according to claim 9, the first combinational circuit defined by the next state, sum-of-product logical equations with maximum (m+s) inputs, maximum s outputs and maximum q1 product terms p(k) in each said next state equation, and the second combinational circuit defined by the output sum-of-product logical equations, with maximum s inputs, maximum r outputs and maximum q2 product terms p(k) in each said output equation;

and further comprising;

a state register with s bits, wherein said state register is the input register of the second combinational circuit;

a feedback connection to establish the next state.