Data processing system having a serial data controller

• US 7,047,350 B2
• Filed: 10/10/2003
• Issued: 05/16/2006
• Est. Priority Date: 10/10/2003
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Vaglica, John J., Elledge, Mark E., Bhaskaran, Sreedharan, Deng, Allen Guoyuan
• Primary Examiner(s): Vo, Tim
• Assistant Examiner(s): KNOLL, CLIFFORD H
• Application Number:
  US10/683,778
• Publication Number:
  US 20050080975A1
• Time in Patent Office: 949 Days
• Field of Search: 710/316, 710/317, 370/357, 370/387, 370/388, 370/389, 370/366
• US Class Current: 710/317
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A data processing system (30) includes two processors (70, 80) and a serial data controller (36) for selectively multiplexing serial data signals between one or more of a plurality of serial data devices (40, 42, 44, 46, 74, 76, 82) The serial data controller (36) includes one or more host ports (50, 52, 54) and one or more peripheral ports (56, 58, 60, 62) coupled together through a switching matrix (64). A control circuit (66) and a plurality of control registers (68) are used to configure and control a serial data path created between two or more ports including clock and frame synchronization timing of the data path.

Claims

1. An apparatus comprising:

at least three serial devices;

a serial data controller comprising;

at least three serial ports, each serial device being coupled to one of the serial ports and each serial port comprising timing and frame synchronization selector logic coupled to receive and transmit timing signals and frame synchronization signals for controlling timing and frame synchronization of a data transmission from any one of the at least three serial ports to another one of the at least three serial ports;

a plurality of data paths including at least a first data path and a second data path, each data path having a first end portion coupled to one of the serial ports and a second end portion coupled to another one of the serial ports, a first one of the serial ports being coupled to a second one of the serial ports via the first data path and to a third one of the serial ports via the second data path; and

control circuitry for dynamically selecting one or more of the data paths for transmission of serial data from a transmitting serial device to a selected subset of the serial devices and not to a deselected subset of the serial devices, wherein the data remains in a serial format throughout the transmission from the transmitting serial device to the selected serial devices.

2. The apparatus of claim 1 wherein the plurality of data paths comprises a third data path, the second one of the serial ports being coupled to the third one of the serial ports via the third data path.

3. The apparatus of claim 1 wherein serial data may be dynamically selectively transmitted from any one of the serial devices to any other of the serial devices via a corresponding one of the data paths.

4. The apparatus of claim 1 wherein the at least three serial devices are comprised within at least two integrated circuits.

5. The apparatus of claim 1 wherein a first serial port comprises:

receive data logic for receiving serial data from each other serial port and for selecting serial data from one of the other serial ports; and

data reversal logic coupled to receive the selected serial data from the receive data logic and coupled to receive and provide serial data from and to a first serial device coupled to the first serial port.

6. The apparatus of claim 5 wherein the apparatus comprises a plurality of control registers coupled to provide control signals to the timing selector logic, the data reversal logic and the receive data logic, the content of the control registers being definable through software.

7. The apparatus of claim 5 wherein the timing signals and frame synchronization signals are transmitted between each of the at least three serial ports separately from the data transmission.

8. The apparatus of claim 5 wherein the receive data logic comprises:

a receive data selection circuit coupled to receive a serial data signal from each of the other serial ports and coupled to provide a selected one of the serial data signals; and

a buffer enable selection circuit coupled to receive a buffer enable signal from each of the serial ports of the serial data controller and for providing a selected buffer enable signal to the data reversal logic of the corresponding serial port.

9. The apparatus of claim 8 wherein the apparatus further comprises network mode logic, the network mode logic comprising:

a plurality of control registers coupled to provide at least one network mode mask control signal to the network mode logic; and

a network mode selection circuit coupled to receive the serial data signals from the other serial ports and coupled to provide a selected one of the serial data signals under control of the at least one network mode mask control signal.

10. The apparatus of claim 9 wherein the receive data logic further comprises:

a multiplexer coupled to receive the selected serial data signal from the network mode logic at a first input, the selected serial data signal from the receive data selection circuit at a second input, a receive mode control signal at a control input to select an output signal depending on an indication of whether the selected serial data is being transmitted in network mode or in a point-to-point mode.

11. The apparatus of claim 8 wherein the data reversal logic comprises:

first and second buffers coupled to provide serial data to the first serial device;

a first demultiplexer coupled to receive the selected serial data from the receive data logic and coupled to provide the selected serial data to a selected one of the first and second buffers;

a second demultiplexer coupled to receive the selected buffer enable signal from the receive data logic and coupled to provide the selected buffer enable signal to a selected one of the first and second buffers.

12. The apparatus of claim 8 wherein the receive data selection circuit comprises a first multiplexer coupled to receive a static port select control signal from a control register at a control input, the apparatus further comprising a second multiplexer coupled to receive a dynamic port select control signal at a control input, the selected serial data from the first multiplexer at a first data input, and a serial data from a predetermined serial port at a second data input.

13. The apparatus of claim 9 wherein the first serial port is a host serial port configurable for network mode communication from a host serial device to a plurality of serial devices, the apparatus further comprising a peripheral serial port configurable for point-to-point mode communication from a corresponding peripheral serial device to a selected other serial device, the peripheral serial port comprising:

timing selector logic coupled to receive and transmit message timing signals corresponding to messages sent from each of the serial devices;

receive data logic for receiving serial data from each other serial port and for selecting serial data from one of the other serial ports; and

data reversal logic coupled to receive the selected serial data from the receive data logic and coupled to receive and provide serial data from and to the peripheral serial device.

14. In a system including at least three serial devices and a serial data controller, each serial device being coupled to each other serial device via a corresponding data path of the serial data controller, a method for communicating serial data, the method comprising:

providing at least three serial ports, each serial device being coupled to one of the at least three serial ports;

dynamically selecting one or more of the data paths for transmission of serial data from a transmitting serial port to a selected subset of the serial port;

dynamically deselecting one or more of the data paths to prevent transmission of serial data from the transmitting serial port to a deselected subset of serial ports;

providing timing and frame synchronization signals from any one of the at least three serial ports for clocking and synchronizing the transmission of serial data from the transmitting port to the selected serial ports; and

transmitting the serial data from the transmitting serial port to the selected serial ports such that the serial data remains in a serial format throughout the transmission from the transmitting serial device to the selected serial devices.

15. The method of claim 14 further comprising:

selecting one data path for transmission of serial data during a point-to-point mode transmission; and

selecting multiple data paths for transmission of serial data from a transmitting serial device to a plurality of serial devices during a network mode transmission.

27. The method of claim 14, further comprising:

dynamically selecting at least one of the serial devices for participation in a time division multiplexed network; and

dynamically deselecting at least one of the serial devices from participation in the time-division-multiplexed network.

28. The method of claim 27 further comprising the steps of:

dynamically selecting a clock master device from among the serial devices; and

dynamically selecting a frame synchronization master device from among the serial devices.

29. The method of claim 27 further comprising the step of dynamically selecting a network master from among the serial devices.

30. The method of claim 27 further comprising the step of transmitting serial data from a first serial devices to a second serial devices without submitting a request from the first serial data source to a third serial data source.

16. An apparatus comprising:

at least three serial devices, each of the serial devices configured to transmit serial data at a corresponding clock rate, wherein at least two of the serial devices are configured to transmit at different clock rates;

a serial data controller comprising;

at least three serial ports, each serial device being coupled to one of the serial ports, each serial port for providing the serial data at the corresponding clock rate during a data transmission of the serial data; and

a plurality of data paths, each data path having a first end portion coupled to one of the serial ports and a second end portion coupled to another one of the serial ports, wherein the serial data may be dynamically selectively transmitted from any of the serial devices to any other of the serial devices via a corresponding one of the data paths to the exclusion of deselected serial devices, wherein the data remains in a serial format throughout the transmission from the transmitting serial device to the receiving serial device.

17. The apparatus of claim 16 wherein the plurality of serial devices comprises:

a host serial data source, the host serial data source comprising

a processor; and

a memory coupled to the processor via a bus; and

a plurality of peripheral serial data sources, each of the peripheral serial data sources being selectively coupled to any of the host serial data sources in any of a plurality of dynamically selectable network mode configurations.

18. The apparatus of claim 16 wherein the host serial data sources and at least a first set of the peripheral serial data sources are comprised within a wireless communication device.

19. The apparatus of claim 16 wherein the serial data controller comprises clock and frame synchronization selection logic for dynamically selecting a first one of the plurality of serial data source devices to provide a frame sync signal for a serial data transfer and for dynamically selecting a second one of the plurality of serial data source devices to provide a clock signal for the serial data transfer.

20. The apparatus of claim 16 wherein the serial data controller comprises data reversal logic for dynamically reconfiguring a receive data path as a transmit data path, and a transmit data path as a receive data path.

21. The apparatus of claim 16 wherein each serial port comprises:

clock and frame synchronization selection logic for dynamically selecting which of the plurality of serial data source devices provides a frame sync signal for a serial data transfer and for dynamically selecting which of the plurality of serial data source devices provides a clock signal for the serial data transfer;

data reversal logic for reversing receive and transmit data paths through the serial port; and

receive data logic for selecting one of the other serial ports from which to receive data.

22. The apparatus of claim 21 wherein at least one of the serial ports comprises network mode logic coupled to receive serial data signals from others of the serial ports and coupled to provide a selected one of the serial data signals under control of a network mode mask control signal.

23. The apparatus of claim 16 wherein each serial port comprises a plurality of control registers for storing data path selection information.

24. A special purpose audio information steering circuit comprising:

a plurality of serial I/O ports, wherein each of the I/O ports is configured to couple to a corresponding serial device, and wherein each of the I/O ports is coupled to each of the other I/O ports via a point-to-point data path through which audio information may be transmitted from a first serial device to a second serial device each serial I/O port comprising timing and frame synchronization selector logic coupled to receive and transmit timing signals and frame synchronization signals for controlling timing and frame synchronization of an audio data transmission from any one of the plurality of serial I/O ports to another one of the plurality of serial I/O parts; and

control circuitry for dynamically selecting one or more of the data paths for transmission of audio data from an I/O port receiving audio data to a selected subset of the I/O ports and not to a deselected subset of the I/O ports, wherein the audio data remains in a serial format throughout the transmission from the receiving I/O port to the selected I/O ports.

25. A special purpose audio information steering circuit comprising:

a plurality of serial ports, the plurality of serial ports including

N host ports configured to receive data from multiple serial sources in a TDM network mode, each of the N host serial ports comprising timing and frame synchronization selector logic coupled to receive and transmit timing signals and frame synchronization signals for controlling timing and frame synchronization of a data transmission from any of the plurality of serial ports; and

M peripheral ports configured to receive data from a single selectable serial source, each of the M peripheral ports comprising timing and frame synchronization selector logic coupled to receive and transmit timing signals and frame synchronization signals for controlling timing and frame synchronization of a data transmission from any of the plurality of serial ports;

a software configurable serial interface block coupled to each of the host ports and the peripheral ports, the interface block including M×

N data paths, each data path being coupled between a host and a peripheral; and

control registers for storing control information to dynamically select one or more of the data paths for transmission of audio data from a first selected subset of the serial ports to a second selected subset of the serial ports and not to a deselected subset of the serial ports, wherein the audio data remains in a serial format throughout the transmission from the first subset of serial ports to the second subset of serial ports.

26. The special purpose audio information steering circuit of claim 25 wherein the control registers are configured to store control information for selecting a mode of communication, the first subset and the second subset each include one selected serial port during a selected point-to-point communication and the first subset including at least one serial port during a selected network mode communication.