Memory hub bypass circuit and method

• US 7,047,351 B2
• Filed: 01/21/2005
• Issued: 05/16/2006
• Est. Priority Date: 08/16/2002
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Jeddeloh, Joseph M.
• Primary Examiner(s): Peugh, Brian R.
• Application Number:
  US11/041,071
• Publication Number:
  US 20050132159A1
• Time in Patent Office: 480 Days
• Field of Search: 711/169, 711/168, 711/167, 711/5, 711/101, 711/154, 711/105, 711/202, 711/211, 711/220, 365/230.08, 365/230.06, 365/230.05, 365/230.03, 365/230.02, 365/185.11
• US Class Current: 711/5
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1642 with request queuing
• CPC Class Codes: G06F 13/1684 using multiple buses

Abstract

A computer system and a method used to access data from a plurality of memory devices with a memory hub. The computer system includes a plurality of memory modules coupled to a memory hub controller. Each of the memory modules includes the memory hub and the plurality of memory devices. The memory hub includes a sequencer and a bypass circuit. When the memory hub is busy servicing one or more memory requests, the sequencer generates and couples the memory requests to the memory devices. When the memory hub is not busy servicing multiple memory requests, the bypass circuit generates and couples a portion of each the memory requests to the memory devices and the sequencer generates and couples the remaining portion of each of the memory requests to the memory devices.

Claims

1. A memory module, comprising:

a plurality of memory devices; and

a memory hub, comprising;

a link interface operable to receive memory requests for access to at least one of the memory devices;

a memory device interface operable to couple memory requests to the plurality of memory devices; and

a memory request processing system coupled to the link interface and the memory device interface, the memory request processing system being operable responsive to receiving a memory request to determine whether or not at least one other memory request is being serviced by the memory module, the memory request processing system being operable responsive to determining that the at least one other memory request is not being serviced to cause a portion of a memory request corresponding to the memory request received by the memory request processing system to be transferred to the memory device interface, the memory request processing system further being operable responsive to determining that the at least one other memory request is being serviced to schedule at least a portion of the memory request corresponding to the memory request received by the memory request processing system to be subsequently transferred to the memory device interface.

2. The memory module of claim 1 wherein the memory request processing system is operable to determine whether or not at least one memory request is being serviced by the memory device interface.

3. The memory module of claim 1 wherein the memory request processing system comprises:

a bypass circuit coupled to the link interface and the memory device interface, the bypass circuit causing a portion of the memory request corresponding to the memory request received by the memory request processing system to be transferred to the memory device interface responsive to determining that the at least one other memory request is not being serviced; and

a sequencer coupled to the link interface and the memory device interface, the sequencer scheduling the memory request corresponding to the at least one memory request received by the memory request processing system to be subsequently transferred to the memory device interface responsive to determining that the at least one other memory request is being serviced.

4. The memory module of claim 3 wherein the memory request processing system is further operable to cause any remaining portion of the memory request corresponding to the memory request received by the memory request processing system that is not handled by the bypass circuit to be coupled to the memory device interface responsive to the memory request processing system determining that the at least one other memory request is not being serviced.

5. The memory module of claim 3 wherein, in response to the memory request processing system determining that the at least one other memory request is not being serviced, the bypass circuit is operable responsive to transfer to the memory device interface a row address corresponding to a row address in the memory request received by the memory request processing system, and the sequencer is operable to transfer to the memory device interface remaining portions of the memory request corresponding to the memory request received by the memory request processing system.

6. The memory module of claim 1 wherein the memory device interface comprises a first-in, first-out buffer that is operable to receive and store memory requests received from the link interface.

7. The memory module of claim 1 wherein the memory device interface is coupled to the link interface, the memory device interface further receiving read data responsive to the memory requests received by the memory request processing system and coupling the read data to the link interface.

8. The memory module of claim 1 wherein the link interface comprises an optical input/output port.

9. The memory module of claim 1 wherein the memory request processing system is operable to reformat memory requests received by the link interface before causing memory requests to be transferred to the memory device interface.

10. The memory module of claim 1 wherein the memory devices comprises dynamic random access memory devices.

11. The memory module of claim 1 wherein the memory request processing system is operable responsive to determining that the at least one other memory request is not being serviced to initially transfer to the memory device interface a row address corresponding to a row address in the memory request received by the memory request processing system and to subsequently transfer to the memory device interface remaining portions of the memory request corresponding to the memory request received by the memory request processing system.

12. A memory hub, comprising:

a link interface operable to receive memory requests for access to at least one of the memory devices;

a memory device interface operable to couple memory requests to the memory devices; and

a memory request processing system coupled to the link interface and the memory device interface, the memory request processing system being operable responsive to receiving a memory request to determine whether or not at least one other memory request is being serviced by the memory module, the memory request processing system being operable responsive to determining that the at least one other memory request is not being serviced to cause a portion of a memory request corresponding to the memory request received by the memory request processing system to be transferred to the memory device interface, the memory request processing system further being operable responsive to determining that the at least one other memory request is being serviced to schedule at least a portion of at least one memory request corresponding to the memory request received by the memory request processing system to be subsequently transferred to the memory device interface.

13. The memory hub of claim 12 wherein the memory request processing system is operable to determine whether or not the at least one other memory request is being serviced by the memory device interface.

14. The memory hub of claim 12 wherein the memory request processing system comprises:

a bypass circuit coupled to the link interface and the memory device interface, the bypass circuit causing a portion of the memory request corresponding to a memory request received by the memory request processing system to be transferred to the memory device interface responsive to determining that the at least one other memory request is not being serviced; and

a sequencer coupled to the link interface and the memory device interface, the sequencer scheduling the memory request corresponding to the memory request received by the memory request processing system to be subsequently transferred to the memory device interface responsive to determining that the at least one other memory request is being serviced.

15. The memory hub of claim 14 wherein the memory request processing system is further operable to cause any remaining portion of the memory request not handled by the bypass circuit to be coupled to the memory device interface responsive to the memory request processing system determining that the at least one other memory request is not being serviced.

16. The memory hub of claim 14 wherein, in response to the memory request processing system determining that the at least one other memory request is not being serviced, the bypass circuit is operable responsive to transfer to the memory device interface a row address corresponding to a row address in the memory request received by the memory request processing system, and the sequencer is operable to transfer to the memory device interface remaining portions of the memory address corresponding to the memory request received by the memory request processing system.

17. The memory hub of claim 12 wherein the memory device interface comprises a first-in, first-out buffer that is operable to receive and store memory requests received from the link interface.

18. The memory hub of claim 12 wherein the memory device interface is coupled to the link interface, the memory device interface further receiving read data responsive to the memory requests and coupling the read data to the link interface.

19. The memory hub of claim 12 wherein the link interface comprises an optical input/output port.

20. The memory hub of claim 12 wherein the memory request processing system is operable to reformat memory requests received by the link interface before causing memory requests to be transferred to the memory device interface.

21. The memory hub of claim 12 wherein the memory requests received by the link interface comprise dynamic random access memory requests.

22. The memory hub of claim 12 wherein the memory requests transmitted by the memory device interface comprise dynamic random access memory requests.

23. The memory hub of claim 12 wherein the memory request processing system is operable responsive to determining that the at least one other memory request is not being serviced to initially transfer to the memory device interface a row address corresponding to a row address in the memory request received by the memory request processing system and to subsequently transfer to the memory device interface remaining portions of the memory request corresponding to the memory request received by the memory request processing system.

24. A processor-based system, comprising:

a central processing unit (“

CPU”

);

a system controller coupled to the CPU, the system controller having an input port and an output port;

an input device coupled to the CPU through the system controller;

an output device coupled to the CPU through the system controller;

a storage device coupled to the CPU through the system controller; and

a plurality of memory modules, each of the memory modules comprising;

a plurality of memory devices; and

a memory hub, comprising;

a link interface operable to receive memory requests for access to at least one of the memory devices;

a memory device interface operable to couple memory requests to the plurality of memory devices; and

a memory request processing system coupled to the link interface and the memory device interface, the memory request processing system being operable responsive to receiving a memory request to determine whether or not at least one other memory request is being serviced by the memory module, the memory request processing system being operable responsive to determining that the at least one other memory request is not being serviced to cause a portion of a memory request corresponding to the memory request received by the memory request processing system to be transferred to the memory device interface, the memory request processing system further being operable responsive to determining that the at least one other memory request is being serviced to schedule at least a portion of the memory request corresponding to the memory request received by the memory request processing system to be subsequently transferred to the memory device interface.

25. The processor-based system of claim 24 wherein the memory request processing system is operable to determine whether or not at least one memory request is being serviced by the memory device interface.

26. The processor-based system of claim 24 wherein the memory request processing system comprises:

a bypass circuit coupled to the link interface and the memory device interface, the bypass circuit causing a portion of the memory request corresponding to the memory request received by the memory request processing system to be transferred to the memory device interface responsive to determining that the at least one other memory request is not being serviced; and

a sequencer coupled to the link interface and the memory device interface, the sequencer scheduling the memory request corresponding to the at least one memory request received by the memory request processing system to be subsequently transferred to the memory device interface responsive to determining that the at least one other memory request is being serviced.

27. The processor-based system of claim 26 wherein the memory request processing system is further operable to cause any remaining portion of the memory request corresponding to the memory request not handled by the bypass circuit to be coupled to the memory device interface responsive to the memory request processing system determining that the at least one other memory request is not being serviced.

28. The processor-based system of claim 26 wherein, in response to the memory request processing system determining that the at least one other memory request is not being serviced, the bypass circuit is operable responsive to transfer to the memory device interface a row address corresponding to a row address in the memory request received by the memory request processing system, and the sequencer is operable to transfer to the memory device interface remaining portions of the memory request corresponding to the memory request received by the memory request processing system.

29. The processor-based system of claim 24 wherein the memory device interface comprises a first-in, first-out buffer that is operable to receive and store memory requests received from the link interface.

30. The processor-based system of claim 24 wherein the memory device interface is coupled to the link interface, the memory device interface further receiving read data responsive to the memory requests received by the memory request processing system and coupling the read data to the link interface.

31. The processor-based system of claim 24 wherein the link interface comprises an optical input/output port.

32. The processor-based system of claim 24 wherein the memory request processing system is operable to reformat memory requests received by the link interface before causing memory requests to be transferred to the memory device interface.

33. The processor-based system of claim 24 wherein the memory devices comprise dynamic random access memory devices.

34. The processor-based system of claim 24 wherein the memory request processing system is operable responsive to determining that the at least one other memory request is not being serviced to initially transfer to the memory device interface a row address corresponding to a row address in the memory request received by the memory request processing system and to subsequently transfer to the memory device interface remaining portions of the memory request corresponding to the memory request received by the memory request processing system.