Fail-safe method of updating a multiple FPGA configuration data storage system

• US 7,047,352 B1
• Filed: 08/28/2002
• Issued: 05/16/2006
• Est. Priority Date: 08/28/2002
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Khu, Arthur H., Shokouhi, Farshid
• Primary Examiner(s): BATAILLE, PIERRE MICHE
• Application Number:
  US10/230,920
• Time in Patent Office: 1,357 Days
• Field of Search: 711/103, 711/205, 711/154, 711/170, 713/100, 713/400, 713/1, 326/38, 365/200, 370/467
• US Class Current: 711/103
• CPC Class Codes: G06F 11/1441 Resetting or repowering
• CPC Class Codes: G06F 12/1425 the protection being physical, e.g. cell, word, block
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: H03K 19/17764 for reliability
• CPC Class Codes: H03K 19/17772 for powering on or off

Abstract

Structure and method for updating a system that includes a memory and a programmable logic device (PLD) retains a default PLD configuration in the memory while a new configuration is being stored in the memory, and thus protect the system from failure in case an interruption occurs while the new configuration is being stored. If a power failure interrupts the storing process, the default PLD configuration is still in the memory and can be re-loaded into the PLD and used when the system is re-started to make a further attempt at storing the new configuration. Methods are also disclosed for storing in the memory a configuration for a new PLD before the original PLD is replaced so that system hardware can be updated with minimum effort and disruption, and for dividing a directory structure into protected and unprotected regions.

Claims

1. A reconfigurable system comprising:

a computer readable memory divided into sectors and including a directory, wherein the directory includes a plurality of pointers that reference the sectors, respectively;

a programmable logic device (PLD);

a structure for identifying a default pointer in the directory; and

a circuit for programming the PLD with data from a part of the memory identified by the default pointer;

wherein the circuit is configured to program the PLD with the data from the part of the memory identified by the default pointer if an error occurs when storing an alternative configuration in the memory.

2. The system of claim 1 wherein the structure for identifying the default pointer is a jumper manually movable by a user.

3. The system of claim 1 wherein the circuit for programming the PLD with data from a part of the memory identified by the default pointer is further able to program the PLD with data from a part of the memory not identified by the default pointer.

4. The system of claim 1 wherein the structure for identifying the default pointer is a controller.

5. The system of claim 1 wherein the structure for identifying the default pointer is a microprocessor.

6. The system of claim 1, wherein the sectors of the computer readable memory comprise:

at least one default sector for storing a default programmable logic device (PLD) configuration;

at least one alternative sector for storing an alternative PLD configuration;

a directory sector storing the directory.

7. The system of claim 6, wherein the default PLD configuration is stored in more than one default sector.

8. The system of claim 7, wherein the alternative PLD configuration is stored in more than one alternative sector and occupies as much of the memory as does the default PLD configuration.

9. The system of claim 6, wherein the alternative PLD configuration occupies an amount of memory different from an amount of memory occupied by the default PLD configuration.

10. The system of claim 6, wherein the at least one alternative sector comprises a plurality of alternative sectors.

11. The system of claim 6, wherein the pointers each point to a starting address for a configuration.

12. The system of claim 11, wherein the starting addresses are separated from each other by an amount greater than the memory required for the default configuration.

13. A method for programming a programmable logic device (PLD) comprising:

storing a directory in a memory, the directory including a plurality of pointers that reference a plurality of sectors of the memory, respectively;

storing default data in a first sector, the first sector being any of the plurality of sectors of the memory;

setting a first one of the pointers in the directory to reference the default data in the first sector;

programming the PLD with the default data referenced by the first one of the pointers;

storing alternative data in a second sector, the second sector being any of the sectors other than the first sector of the memory;

if storing the alternative data was successful,

setting a second one of the pointers in the directory to point to the alternative data in the second sector; and

programming the PLD with the alternative data referenced by the second one of the pointers;

if storing the alternative data was not successful, programming the PLD with the default data referenced by the first one of the pointers.

14. The method of claim 13, further comprising reading one of the pointers from the directory in response to an address provided by a device external to the memory;

and

using the one of the pointers to reference data for programming the PLD.

15. A computer memory structure comprising:

at least one region of memory for storing a default PLD configuration;

at least one alternative region of memory for storing an alternative PLD configuration;

a region of memory storing a directory;

at least one region of memory storing a plurality of information blocks;

wherein the directory comprises a plurality of pointers to a corresponding plurality of information blocks and each of the information blocks points to one of the regions of memory for storing a PLD configuration;

wherein the at least one region of memory storing a plurality of information blocks comprises at least two regions of memory, one of which stores a default information block and one of which stores alternative information blocks; and

wherein the region of memory storing a directory, the region of memory for storing a default PLD configuration, and the region of memory which stores a default information block are protected from being overwritten.

16. The computer memory structure of claim 15 wherein the default and alternative information blocks store information on size and starting address for corresponding PLD configurations.

17. The computer memory structure of claim 16 wherein the information blocks further store additional information on the corresponding PLD configurations.

18. A method of updating an electronic system having an original programmable logic device (PLD) and a memory, the method comprising:

storing an alternative PLD configuration for an alternative PLD in the memory;

confirming that the alternative PLD configuration was stored correctly;

replacing the original PLD with an alternative PLD; and

configuring the alternative PLD with the alternative PLD configuration;

wherein replacing the original PLD with an alternative PLD comprises;

removing the original PLD from the system; and

placing an alternative PLD in a position occupied by the original PLD in the system; and

wherein confirming that the alternative PLD configuration was stored correctly comprises;

if the alternative PLD configuration was stored correctly, indicating that the alternative PLD configuration was stored correctly;

if the alternative PLD configuration was not stored correctly,

assuring that the default configuration is loaded into the old PLD, and

again storing the alternative PLD configuration in the memory; and

repeating the steps of indicating assuring and again storing until the alternative PLD configuration is stored correctly.

19. The method of claim 18 wherein the step of confirming that the alternative PLD configuration was stored correctly comprises:

recognizing that the alternative PLD configuration was not stored correctly;

restoring an original PLD configuration to the original PLD; and

repeating the step of storing an alternative PLD configuration.

20. The method of claim 18 wherein replacing the original PLD with an alternative PLD comprises:

powering down the system;

while the system is without power, removing the original PLD and inserting the alternative PLD; and

powering up the system.

21. The method of claim 18 wherein replacing the original PLD with an alternative PLD comprises:

removing a board including the original PLD from the system; and

replacing the board in the system.

22. The method of claim 21 wherein the steps of removing a board including the original PLD from the system and replacing the board in the system are separated by replacing a PLD on the board.

23. The method of claim 21 wherein the steps of removing a board including the original PLD from the system and replacing the board in the system are separated by substituting another board for the board.

24. The method of claim 18 wherein configuring the alternative PLD with the alternative PLD configuration comprises addressing a directory in the memory to select a pointer to the alternative PLD configuration.