Memory reallocation and sharing in electronic systems

• US 7,047,368 B2
• Filed: 10/28/2003
• Issued: 05/16/2006
• Est. Priority Date: 09/02/2003
• Status: Expired due to Fees

• Current Assignee: CSR Technology Incorporated (Qualcomm, Inc.)
• Original Assignee: SIRF Technology Incorporated (Qualcomm, Inc.)
• Inventors: Gronemeyer, Steven A., Protic, Vojislav, Vantalon, Nicolas P.
• Primary Examiner(s): Padmanabhan, Mano
• Assistant Examiner(s): Walter, Craig E
• Application Number:
  US10/696,522
• Publication Number:
  US 20050050282A1
• Time in Patent Office: 931 Days
• Field of Search: None
• US Class Current: 711/147
• CPC Class Codes: G01S 19/215 issues related to spoofing
• CPC Class Codes: G01S 19/246 involving long acquisition integration times, extended snapshots of signals or methods specifically directed towards weak signal acquisition
• CPC Class Codes: G01S 19/29 carrier including Doppler, related G01S19/246 takes precedence
• CPC Class Codes: G01S 19/30 code related G01S19/246 takes precedence
• CPC Class Codes: G01S 19/37 Hardware or software details of the signal processing chain
• CPC Class Codes: G06F 12/0223 User address space allocation, e.g. contiguous or non contiguous base addressing
• CPC Class Codes: G06F 12/0284 Multiple user address space allocation, e.g. using different base addresses interprocessor communication G06F15/163
• CPC Class Codes: G06F 9/544 Buffers; Shared memory; Pipes
• CPC Class Codes: H04B 1/7075 with code phase acquisition
• CPC Class Codes: H04B 1/7097 Interference-related aspects
• CPC Class Codes: H04B 1/7107 Subtractive interference cancellation
• CPC Class Codes: H04B 2201/70715 with application-specific features

Abstract

Memory reallocation and sharing among components of an electronic system is provided. The electronic system includes a first memory area coupled for access by a first processor via a first bus, and a second memory area coupled for access by a second processor via a second bus. An example system includes a central processor as the first processor and a digital signal processor as the second processor. The electronic system further includes memory configurations that support shared access of the second memory area by the first processor. Using shared access, the first processor can directly access the second memory via the first bus or indirectly access the second memory via the second bus and the second processor. The memory sharing also includes partitioning the shared memory to simultaneously provide the first processor with direct and indirect access to the shared memory.

Claims

1. A device comprising:

a central processor and at least one coprocessor coupled to at least one bus;

a memory device coupled to the at least one bus; and

at least one register coupled to the at least one bus and including information for use in controlling at least one configuration of the memory device in response to system state information, a first configuration supporting direct access to the memory device exclusively by the at least one coprocessor, a second configuration supporting at least one of direct access to a first area of the memory device by the at least one coprocessor and indirect access to a second area of the memory device by the central processor, and a third configuration supporting at least one of direct access to the first area of the memory device by the at least one coprocessor and direct access to a third area of the memory device by the central processor.

2. The device of claim 1, further comprising at least one decoder coupled to the at least one bus, the at least one decoder using address information on the at least one bus to select one of the memory areas to receive data corresponding to the address information.

3. The device of claim 1, further comprising at least one bridge unit that couples the at least one coprocessor and the memory device to a first bus, wherein the indirect access to the memory device by the central processor includes mapping at least one set of memory locations of the memory device through the at least one bridge unit for access by the central processor.

4. The device of claim 1, further comprising at least one memory interface that couples the memory device to a first bus, wherein the direct access to the memory device by the central processor includes mapping at least one set of memory locations of the memory device through the at least one memory interface for access by the central processor.

5. The device of claim 1, wherein the central processor is clocked at a first speed and the at least one coprocessor is clocked at a second speed.

6. The device of claim 1, wherein the at least one bus includes:

a first bus coupling the central processor to a bridge unit;

a second bus coupling the at least one bridge unit to the at least one coprocessor and the memory device.

7. The device of claim 1, wherein the device includes at least one of cellular telephones, portable position tracking devices, and cellular telephones coupled to position tracking devices.

8. A portable electronic apparatus comprising:

a central processor;

a signal processor;

a first memory area coupled for access by the central processor via a first bus;

a second memory area coupled for access by the signal processor via a second bus; and

at least one component coupled to the central processor that controls shared access to the second memory area by the central processor, the shared access including access by the signal processor and at least one of indirect access by the central processor to at least one set of memory locations of the second memory area via the second bus and direct access by the central processor to a set of memory locations of the second memory area via the first bus.

9. A method comprising:

receiving state information associated with an electronic system; and

configuring a memory device using at least one configuration in response to the state information, a first configuration supporting direct access to the memory device exclusively by a coprocessor, a second configuration supporting at least one of direct access to a first area of the memory device by the coprocessor and indirect access to a second area of the memory device by a central processor, and a third configuration supporting at least one of direct access to the first area of the memory device by the coprocessor and direct access to a third area of the memory device by the central processor.

10. The method of claim 9, further comprising:

receiving address information associated with data of the electronic system;

decoding the address information; and

selecting one of the areas of the memory device to receive the data in response to the decoded address information.

11. The method of claim 9, further comprising mapping at least one set of memory locations of the memory device through a first interface to provide the indirect access to the memory device by the central processor.

12. The method of claim 9, further comprising mapping at least one set of memory locations of the memory device through a second interface to provide the direct access to the memory device by the central processor.

13. The method of claim 9, further comprising:

clocking the direct access at a first clock speed; and

clocking the indirect access at a second clock speed.

14. A computer readable medium including executable instructions which, when executed in a processing system, cause the system to:

receive state information associated with an electronic system; and

configure a memory device using at least one configuration in response to the state information, a first configuration supporting direct access to the memory device exclusively by a coprocessor, a second configuration supporting at least one of direct access to a first area of the memory device by the coprocessor and indirect access to a second area of the memory device by a central processor, and a third configuration supporting at least one of direct access to the first area of the memory device by the coprocessor and direct access to a third area of the memory device by the central processor.