Computer for execution of RISC and CISC instruction sets
First Claim
1. A computer, comprising:
- a general register file of registers;
a RISC instruction decoder exposed for execution of user-state programs in a RISC instruction set, being an instruction set having fixed-length instructions and a load/store/operate organization; and
a hardware CISC instruction decoder exposed for execution by user-state programs in a CISC instruction set, being an instruction set with variable-length instructions and many instructions having multiple side-effects, the CISC decoder designed to decode less than the entire CISC instruction set for the computer, and to deliver the decoded instructions to an instruction execution pipeline designed to execute the output of both the RISC instruction decoder and the CISC instruction decoder;
a software emulator programmed to implement a remainder of the instruction set;
the CISC instruction set providing accessibility to only a subset of the registers of the general register file, intermediate results of instructions of the instruction set being stored in registers of the general register file that are inaccessible in the CISC instruction set;
instructions of the RISC instruction set of the RISC decoder having an explicit segment designator field, distinct from a register operand specifier, corresponding to a segment designator field of the CISC instruction set.
3 Assignments
0 Petitions
Accused Products
Abstract
A computer is disclosed. The computer has a general register file of registers, a RISC instruction decoder, and a CISC instruction decoder. The RISC instruction decoder is exposed for execution of user-state programs in a RISC instruction set, being an instruction set having fixed-length instructions and a load/store/operate organization. The hardware CISC instruction decoder is exposed for execution by user-state programs in a CISC instruction set, being an instruction set with variable-length instructions and many instructions having multiple side-effects. The CISC decoder is designed to decode a portion of an instruction set for the computer, and to deliver the decoded instructions to an instruction execution pipeline designed to execute the output of both the RISC instruction decoder and the CISC instruction decoder. A software emulator is programmed to implement a remainder of the instruction set. The CISC instruction set provides accessibility to only a subset of the registers of the general register file, intermediate results of instructions of the instruction set being stored in registers of the general register file that are inaccessible in the CISC instruction set.
485 Citations
72 Claims
-
1. A computer, comprising:
-
a general register file of registers; a RISC instruction decoder exposed for execution of user-state programs in a RISC instruction set, being an instruction set having fixed-length instructions and a load/store/operate organization; and a hardware CISC instruction decoder exposed for execution by user-state programs in a CISC instruction set, being an instruction set with variable-length instructions and many instructions having multiple side-effects, the CISC decoder designed to decode less than the entire CISC instruction set for the computer, and to deliver the decoded instructions to an instruction execution pipeline designed to execute the output of both the RISC instruction decoder and the CISC instruction decoder; a software emulator programmed to implement a remainder of the instruction set; the CISC instruction set providing accessibility to only a subset of the registers of the general register file, intermediate results of instructions of the instruction set being stored in registers of the general register file that are inaccessible in the CISC instruction set; instructions of the RISC instruction set of the RISC decoder having an explicit segment designator field, distinct from a register operand specifier, corresponding to a segment designator field of the CISC instruction set.
-
-
2. A method, comprising the steps of:
-
decoding instructions of a user-state program coded in a RISC instruction set in a hardware instruction decoder of a computer, the RISC instruction set being an instruction set having fixed-length instructions and a load/store/operate organization; and decoding instructions of a user-state program coded in a CISC instruction set in a CISC hardware instruction decoder of a computer, the CISC instruction set being an instruction set having variable-length instructions and many instructions having multiple side-effects; and the instructions decoded by the CISC decoder and RISC decoder being executed in a common execution pipeline; instructions of the RISC instruction set of the RISC decoder having an explicit segment designator field, distinct from a register operand specifier, corresponding to a segment designator field of the CISC instruction set. - View Dependent Claims (3, 4, 5, 6, 7, 8)
-
-
9. A computer, comprising:
-
a RISC instruction decoder exposed for execution of user-state programs in a RISC instruction set, being an instruction set having fixed-length instructions and a load/store/operate organization; and a CISC instruction decoder exposed for execution by user-state programs in a CISC instruction set, being an instruction set with variable-length instructions and many instructions having multiple side-effects; an instruction execution pipeline designed to execute the output of both the RISC instruction decoder and the CISC instruction decoder; instructions of the RISC instruction set of the RISC decoder having an explicit segment designator field, distinct from a register operand specifier, corresponding to a segment designator field of the CISC instruction set. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31)
-
-
32. A method, comprising the steps of:
-
executing a user-state program in a computer comprising a CISC hardware instruction decoder implementing less than an entire architectural definition of a CISC instruction set, a remainder of the CISC instruction set being implemented in a software emulator, the software emulator being coded in a RISC instruction set for execution in a RISC hardware instruction decoder of the computer, instructions of the RISC instruction set of the RISC decoder having an explicit segment designator field, distinct from a register operand specifier, corresponding to a segment designator field of the CISC instruction set. - View Dependent Claims (33, 34, 35, 36, 37, 38)
-
-
39. A computer, comprising:
-
a hardware instruction decoder designed to decode a portion of a CISC instruction set for the computer, and to deliver the decoded instructions to a multi-stage execution pipeline for execution; and a software emulator programmed to implement a remainder of the instruction set, the software emulator being coded in a RISC instruction set for execution in a RISC hardware instruction decoder of the computer, instructions of the RISC instruction set of the RISC decoder having an explicit segment designator field, distinct from a register operand specifier, corresponding to a segment designator field of the CISC instruction set. - View Dependent Claims (40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56)
-
-
57. A method, comprising the steps of:
-
executing a CISC portion of a program coded in a CISC instruction set on a computer having a file of general registers, the CISC instruction set providing accessibility to only a subset of the general register file, intermediate results of instructions of the instruction set being stored in registers of the general register file that are inaccessible in the CISC instruction set; and executing a RISC portion of the program coded in a RISC instruction set of the computer, instructions of the RISC instruction set having an explicit segment designator field, distinct from a register operand specifier, corresponding to a segment designator field of the CISC instruction set. - View Dependent Claims (58, 59, 60)
-
-
61. A computer, comprising:
-
a general register file of registers; a CISC instruction decoder designed to decode instructions of a CISC instruction set of the computer, the instruction set providing accessibility to only a subset of the registers of the general register file, intermediate results of instructions of the instruction set being stored in registers of the general register file that are inaccessible in the instruction set; and a RISC instruction decoder designed to decode a RISC instruction set of the computer, instructions of the RISC instruction set of the RISC decoder having an explicit segment designator field, distinct from a register operand specifier, corresponding to a segment designator field of the CISC instruction set and to have addressability to all registers of the general register file. - View Dependent Claims (62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72)
-
Specification