Gate contacting scheme of a trench MOSFET structure

• US 7,049,668 B1
• Filed: 08/25/1998
• Issued: 05/23/2006
• Est. Priority Date: 08/25/1998
• Status: Expired due to Term

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Hshieh, Fwu-Iuan
• Primary Examiner(s): Nadav, Ori
• Application Number:
  US09/139,935
• Time in Patent Office: 2,828 Days
• Field of Search: 257330-334, 257/401, 438270-274, 438/259, 438/589
• US Class Current: 257/401
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/48464 the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
• CPC Class Codes: H01L 2224/49111 the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 2224/49431 on the semiconductor or solid-state body
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

A trench MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure includes crisscrossing trenches formed in a semiconductor substrate. The trenches include inner surfaces filled with conductive material which is electrically separated from the substrate by insulating material. The conductive material is in contact with an overlying first metal layer through a plurality of first contact openings formed in a first insulating layer which is sandwiched between the first metal layer and the trenches. The conductive material in the trenches and the first metal layer constitute the gate of the MOSFET structure. There is also a second metal layer in contact with a source layer formed in the substrate through a plurality of second contact openings formed in a second insulating layer which is sandwiched between the first metal layer and the second metal layer. The second metal layer and the source layer constitute the source of the MOSFET structure. As arranged, the gate and source of the MOSFET structure are connected through separate metal layers on the semiconductor substrate. Consequently, each metal layer maintains higher conductivity and thus faster frequency response. The semiconductor structure formed in accordance with the invention can also assume a higher packing density with lower power-on resistance.

Claims

1. A semiconductor structure comprising:

a substrate having a major surface;

a plurality of low-resistance trenches formed in said substrate extending from said major surface, some of said low-resistance trenches being orientated in a first direction and others of said low-resistance trenches being orientated in a second direction, each of said low-resistance trenches being filled with conductive material which is electrically separated from said substrate by insulating material, said conductive material comprises polycrystalline silicon;

a first insulating layer disposed on said major surface above said low-resistance trenches, said first insulating layer having a plurality of first contact openings above said low-resistance trenches along said first and second directions, said first insulating layer comprises silicon dioxide;

a first conductive layer having crisscrossing segments disposed above said major surface of said substrate, some of said segments being orientated in said first direction and others of said segments being orientated in said second direction, each of said segments being disposed in substantial alignment and in contact with one of said low-resistance trenches through one of said first openings;

a plurality of low-capacitance trenches disposed in said substrate, each of said low-capacitance trenches being disposed without said first conductive layer disposed thereabove and having a trench width substantially narrower than the corresponding trench width of each of said low-resistance trenches, said low-resistance trenches and said low-capacitance trenches being disposed interposing with each other in said substrates;

a second insulating layer disclosed above said first conductive layer, said second insulating layer having a plurality of second contact openings, said second insulating layer comprises borophosphorous silicon glass;

a second conductive layer disposed above said second insulating layer and in contact with said substrate through said second contact openings, said second conductive layer being substantially rectangular in shape disposed on said major surface of said substrate, wherein said rectangular shape of said second conductive layer having no elongated voids extended therein, thereby allowing bonding wires to be substantially unrestrictively attached onto said second conductive layer, said second conductive layer is plated with copper; and

a source layer disposed in said substrate extending from said major surface, wherein said structure is a MOSFET structure having a source, a drain and a gate, said source includes said source layer, said drain includes said substrate, and said gate includes said low-resistance and low-capacitance trenches.

2. A semiconductor structure comprising:

a substrate having a major surface;

a plurality of low-resistance trenches disposed in said substrate extending from said major surface, some of said low-resistance trenches being orientated in a first direction and others of said low-resistance trenches being orientated in a second direction, each of said low-resistance trenches being filled with conductive material which is electrically separated from said substrate by insulating material;

an insulating layer disposed on said major surface above said trenches, said insulating layer having a plurality of contact openings positioned above said trenches along said first and second directions;

a conductive layer disposed above said insulating layer and in contact with said conductive material in said trenches through said contact openings; and

a plurality of low-capacitance trenches disposed in said substrate, each of said low-capacitance trenches being formed without said conductive layer disposed thereabove and having a trench width substantially narrower than the corresponding trench width of each of said low-resistance trenches, said low-resistance trenches and said low-capacitance trenches being disposed interleaving with each other in said substrate.