Area efficient waveform evaluation and DC offset cancellation circuits

• US 7,049,855 B2
• Filed: 06/28/2001
• Issued: 05/23/2006
• Est. Priority Date: 06/28/2001
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Soumyanath, Krishnamurthy, Franca-Neto, Luiz
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): Nguyen, Hai L.
• Application Number:
  US09/896,345
• Publication Number:
  US 20030001653A1
• Time in Patent Office: 1,790 Days
• Field of Search: 327/307, 327/309, 327/318, 327/319, 327320-322, 327/325, 327/327, 327/328, 327/58, 327/61, 327/62, 327/94, 327/311, 327/91, 327/122, 341/122
• US Class Current: 327/58
• CPC Class Codes: G01R 19/02 Measuring effective values, i.e. root-mean-square values
• CPC Class Codes: G01R 19/04 Measuring peak values or amplitude or envelope of ac or of pulses
• CPC Class Codes: H03F 1/30 Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in differential amplifiers H03F3/45479
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/183 a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number H03L7/1806 takes precedence
• CPC Class Codes: H03L 7/23 with pulse counters or frequency dividers

Abstract

Analog circuits for providing one or more waveform parameters, e.g., the DC offset or average, of an analog input signal. Separate biasing is not necessarily required. Some embodiments comprise field-effect-transistors (FETs) configured in various diode-connected configurations that take advantage of leakage currents through the FETs so that long resistors or large capacitors are not necessarily required. One embodiment comprises two diode-connected FETs to provide an unbiased DC offset voltage of an analog input signal.

Claims

1. A circuit comprising:

an input port having an input signal voltage;

an output port having an output voltage; and

a field-effect-transistor (FET) having a gate, a first terminal, and a second terminal;

wherein the gate and the first terminal are each connected to the input port, and the second terminal is connected to the output port;

wherein the FET has a device width, wherein the FET has a leakage current in excess of 1 micro ampere per micron of device width; and

wherein the output voltage is indicative of a local time-average maximum of the input signal voltage.

2. The circuit as set forth in claim 1, further comprising an output circuit connected to the output port to provide a capacitive load.

3. A method to provide an output voltage indicative of a local time-average maximum of an input signal voltage, the method comprising:

operating a field-effect transistor (FET) in its sub-threshold region when in steady state and the input signal voltage is stationary, the FET having a gate, a first terminal, and a second terminal, wherein the FET has a leakage current in excess of 1 micro ampere per micron of device width, wherein the gate and the first terminal are each connected to an input port, and the second terminal is connected to an output port;

providing the input signal voltage to the input port; and

sampling the output voltage at the output port to provide a local time-average maximum of the input signal voltage.

4. A circuit to provide direct current (DC) offset correction to an input signal voltage, the circuit comprising:

an input port having the input signal voltage;

a field-effect-transistor (FET) having a gate, a first terminal, and a second terminal,

wherein the gate and the first terminal are each connected to the input port, wherein the second terminal has a DC offset correction voltage, wherein the FET has a leakage current in excess of 1 micro ampere per micron of device width to provide the DC offset correction voltage as a local time-average maximum of the input signal voltage; and

a DC offset correction unit responsive to the DC offset correction voltage to subtract the DC offset correction voltage from the input signal voltage.

5. A circuit comprising:

an input port having an input signal voltage;

an output port having an output voltage; and

a field-effect-transistor (FET) having a gate, a first terminal, and a second terminal;

wherein the first terminal is connected to the input port, and the gate and the second terminal are each connected to the output port;

wherein the FET has a device width, wherein the FET has a leakage current in excess of 1 micro ampere per micron of device width; and

wherein the output voltage is a local time-average minimum of the input signal voltage.

6. The circuit as set forth in claim 5, further comprising an output circuit connected to the output port to provide a capacitive load.

7. A method to provide an output voltage indicative of a local time-average minimum of an input signal voltage, the method comprising:

operating a field-effect transistor (FET) in its sub-threshold region when in steady state and the input signal voltage is stationary, the FET having a gate, a first terminal, and a second terminal, wherein the FET has a leakage current in excess of 1 micro ampere per micron of device width, wherein the first terminal is connected to an input port, and the gate and the second terminal are each connected to an output port;

providing the input signal voltage to the input port; and

sampling the output voltage at the output port to provide a local time-average minimum of the input signal voltage.

8. A circuit to provide direct current (DC) offset correction to an input signal voltage, the circuit comprising:

an input port having the input signal voltage;

a field-effect-transistor (FET) having a gate, a first terminal, and a second terminal, wherein the first terminal is connected to the input port, wherein the gate and the second terminal are connected to each other and have a DC offset correction voltage;

wherein the FET has a leakage current in excess of 1 micro ampere per micron of device width to provide the DC offset correction voltage as a local time-average minimum of the input signal voltage; and

a DC offset correction unit responsive to the DC offset correction voltage to subtract the DC offset correction voltage from the input signal voltage.