Asymmetric comparator for low power applications

• US 7,049,857 B2
• Filed: 01/17/2002
• Issued: 05/23/2006
• Est. Priority Date: 01/17/2002
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Styduhar, Mark S.
• Primary Examiner(s): Lam, Tuan T.
• Assistant Examiner(s): Nguyen, Hiep
• Application Number:
  US09/683,552
• Publication Number:
  US 20030132786A1
• Time in Patent Office: 1,587 Days
• Field of Search: 327/63, 327/66, 327/68, 327/72, 327/77, 327/89, 327/544, 327/83, 330/252, 330/253
• US Class Current: 327/63
• CPC Class Codes: H03K 3/3565 Bistables with hysteresis, e.g. Schmitt trigger
• CPC Class Codes: H03K 5/082 with an adaptive threshold
• CPC Class Codes: H03K 5/2481 with at least one differential stage

Abstract

A method and structure for comparing an input signal to a reference signal using a comparator comprises a circuit for setting a trip point of a rising edge of an input signal according to a value of an external voltage reference; and at least two transistors, in the circuit, for setting a trip point of a falling edge of an input signal, according to a width-to-length ratio of the at least two transistors. Moreover, the at least two transistors comprises a first transistor of length (Lx) and a width of (W_x); and a second transistor of length (L_y) and a width of (W_y), wherein the width-to-length ratio equals (W_xL_y)/(W_yL_x). The trip point of a falling edge of an input signal increases (decreases) by increasing (decreasing) the width-to-length ratio.

Claims

1. A comparator cycling between an analog configuration and a digital configuration, said comparator comprising:

at least two transistors;

a plurality of transmission gates coupled to said transistors and adapted to select a reference signal and a comparator output signal for signal selection; and

a plurality of invertors coupled to said plurality of transmission gates, wherein said plurality of inventors are operable to buffer said comparator output signal, wherein the buffered output signal is returned as two signals to control said plurality of transmission gates,

wherein said comparator is set to have a first trip point associated with a rising edge of an input signal according to a value of a positive external voltage reference, and a second trip point associated with a falling edge of said input signal according to a width-to-length ratio of said transistors,

wherein only in said analog configuration one of said transistors is a tail current source transistor, whereby said input signal rises from ground toward a positive power supply voltage, and whereby the rise in said input signal switches said tail current source transistor off,

wherein one of said first or second trip point is set externally from said comparator, and

wherein a majority of a cycle time of said comparator is spent in said digital configuration.

2. The comparator of claim 1, wherein said rise in said input signal causes said comparator to appear as a differential pair in an open loop configuration.

3. The comparator of claim 1, wherein in said digital configuration, said input signal is at an input voltage level greater than a level of said positive external voltage reference.

4. The comparator of claim 3, wherein said input signal causes said comparator to have characteristics of an asymmetric inverting Schmitt trigger.

5. The comparator of claim 1, wherein said transistors comprise:

a first transistor of length (L_x) and a width of (W_x); and

a second transistor of length (L_y) and a width of (W_y),

wherein said width-to-length ratio equals (W_xL_y)/(W_yL_x), and

wherein as said input signal decreases, a switching threshold becomes dependent on said width-to-length ratio.

6. The comparator of claim 1, wherein a level of said second trip point decreases by decreasing said width-to-length ratio.

7. The comparator of claim 1, wherein a level of said second trip point increases by increasing said width-to-length ratio.

8. The comparator of claim 1, wherein said comparator spends approximately 80% of said cycle time in said digital configuration.

9. A comparator cycling between an analog configuration and a digital configuration, said comparator comprising:

a plurality of transistors;

a plurality of transmission gates coupled to said transistors and adapted to select a reference signal and a comparator output signal for signal selection; and

a plurality of invertors coupled to said plurality of transmission gates, wherein said plurality of inventors are operable to buffer said comparator output signal, wherein the buffered output signal is returned as two signals to control said plurality of transmission gates,

wherein said comparator is set to have a first trip point associated with a rising edge of an input signal according to a value of a positive external voltage reference, and a second trip point of a falling edge of the input signal according to a width-to-length ratio of said transistors,

wherein a level of said second trip point is adjustable according to said width-to-length ratio,

wherein only in said analog configuration, said device further comprises a tail current source transistor, whereby said input signal rises from ground toward a positive power supply voltage, and whereby said rise in said input signal switches said tail current source transistor off,

wherein one of said first or second trip point is set externally from said comparator, and

wherein a majority of a cycle time of said comparator is spent in said digital configuration.

10. The comparator in claim 9, wherein said transistors comprises:

a first transistor of length (L_x) and a width of (W_x); and

a second transistor of length (L_y) and a width of (W_y),

wherein said width-to-length ratio equals (W_xL_y)/(W_yL_x), and

wherein as said input signal decreases, a switching threshold becomes dependent on said width-to-length ratio.

11. The comparator of claim 9, wherein the rise in said input signal causes said comparator to appear as a differential pair in an open loop configuration.

12. The comparator of claim 9, wherein in said digital configuration, said input signal is at an input voltage level greater than a level of said positive external voltage reference.

13. The comparator of claim 12, wherein said input signal causes said comparator to have characteristics of an asymmetric inverting Schmitt trigger.

14. The comparator of claim 9, wherein said comparator spends approximately 80% of said cycle time in said digital configuration.

15. A comparator set to have a pair of trip points corresponding to a voltage value of a rising and falling edge of an input signal, wherein said comparator cycles between an analog configuration and a digital configuration by selective selection of said input signal through a plurality of transmission gates, wherein said comparator controls a delay between rising and falling edge transitions at an output signal of said comparator, wherein said comparator controls a pulse width at said output signal of said comparator, wherein one of said trip points is external to said comparator, and wherein a majority of a cycle time of said comparator is spent in said digital configuration.

20. The comparator of claim 15, wherein said comparator spends approximately 80% of said cycle time in said digital configuration.

16. A comparator set to have a pair of trip points corresponding to a voltage value of a rising and falling edge of an input signal, wherein said comparator cycles between an analog configuration and a digital configuration by selective selection of said input signal through a plurality of transmission gates, wherein said comparator controls a delay between rising and falling edge transitions at an output signal of said comparator, wherein said comparator controls a pulse width at said output signal of said comparator, wherein one of said trip points is external to said comparator, wherein a majority of a cycle time of said comparator is spent in said digital configuration, and wherein said analog configuration comprises:

an input signal terminal;

an output signal terminal;

a positive power supply voltage terminal;

a positive external voltage reference terminal;

a tail current source transistor operatively connected to said positive power supply voltage terminal;

a first pair of transistors operatively connected to said tail current source transistor, said input signal terminal, and said positive external voltage reference terminal;

a second pair of transistors operatively connected to said first pair of transistors, wherein said second pair of transistors operate as current mirror load transistors; and

a plurality of invertors operatively connected to said output signal terminal, said first pair of transistors, and said second pair of transistors, wherein said plurality of invertors are operable to buffer said output signal, wherein the buffered output signal is returned as two signals to control said plurality of transmission gates.

18. The comparator of claim 16, wherein in said analog configuration, said input signal rises from ground toward a positive power supply voltage, wherein said rise in said input signal switches said tail current source transistor off.

17. A comparator set to have a pair of trip points corresponding to a voltage value of a rising and falling edge of an input signal, wherein said comparator cycles between an analog configuration and a digital configuration by selective selection of said input signal through a plurality of transmission gates, wherein said comparator controls a delay between rising and falling edge transitions at an output signal of said comparator, wherein said comparator controls a pulse width at said output signal of said comparator, wherein one of said trip points is external to said comparator, wherein a majority of a cycle time of said comparator is spent in said digital configuration, and wherein said digital configuration comprises:

an input signal terminal;

an output signal terminal;

a positive power supply voltage terminal;

a tail current source transistor operatively connected to said positive power supply voltage terminal and said input signal terminal;

a first pair of transistors operatively connected to said tail current source transistor and said input signal terminal;

a current mirror load transistor operatively connected to said input signal source and said first pair of transistors; and

a plurality of invertors operatively connected to said output signal terminal, said first pair of transistors, and said current mirror load transistor, wherein said plurality of invertors are operable to buffer said output signal, wherein the buffered output signal is returned as two signals to control said plurality of transmission gates.

19. The comparator of claim 17, wherein in said digital configuration, said input signal is at an input voltage level greater than a level of said positive external voltage reference.