Ahuja compensation circuit with enhanced bandwidth
First Claim
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1. An Ahuja compensation circuit, comprising:
- first and second transistors, wherein a second terminal of said first transistor communicates with a control terminal of said second transistor;
first, second, and third capacitances, wherein a first end of said first capacitance communicates with said second terminal of said first transistor, a first end of said second capacitance communicates with a first terminal of said second transistor, and a second end of said third capacitance communicates with said first terminal of said second transistor, anda high swing cascode biasing circuit that communicates with said second terminal of said first transistor and a first end of said third capacitance and that includes;
a current biasing circuit that generates a cascode bias and a main bias;
a frequency boosting circuit that receives said cascode bias and said main bias; and
a current mirror circuit that receives said main bias.
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Abstract
An Ahuja compensation circuit includes a feedback loop with a high swing cascode biasing circuit. The high swing cascode biasing circuit includes a frequency boosting circuit. The frequency response of the high swing cascode biasing circuit and the Ahuja compensation circuit are improved by the frequency boosting circuit.
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Citations
38 Claims
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1. An Ahuja compensation circuit, comprising:
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first and second transistors, wherein a second terminal of said first transistor communicates with a control terminal of said second transistor; first, second, and third capacitances, wherein a first end of said first capacitance communicates with said second terminal of said first transistor, a first end of said second capacitance communicates with a first terminal of said second transistor, and a second end of said third capacitance communicates with said first terminal of said second transistor, and a high swing cascode biasing circuit that communicates with said second terminal of said first transistor and a first end of said third capacitance and that includes; a current biasing circuit that generates a cascode bias and a main bias; a frequency boosting circuit that receives said cascode bias and said main bias; and a current mirror circuit that receives said main bias. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A feedback loop in an Ahuja compensation circuit, comprising:
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a first transistor; a first capacitance having a first end that communicates with a first terminal of said first transistor; and a high swing cascode biasing circuit that communicates with a second end of said first capacitance and a control terminal of said first transistor and that includes; a current biasing circuit that generates a cascode bias and a main bias; a frequency boosting circuit that receives said cascode bias and said main bias; and a current mirror circuit that receives said main bias. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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26. A feedback loop in an Ahuja compensation circuit, comprising:
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a first transistor; first capacitance means for providing a first capacitance and having a first end that communicates with a first terminal of said first transistor; and high swing cascode biasing means for communicating with a second end of said first capacitance means and a control terminal of said first transistor and that includes; current biasing means for generating a cascode bias and a main bias; frequency boosting means for receiving said cascode bias and said main bias and for boosting a frequency response of said high swing cascode biasing means; and current mirror means for receiving said main bias. - View Dependent Claims (27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38)
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Specification