Unified analog input front end apparatus and method

• US 7,049,989 B2
• Filed: 10/01/2004
• Issued: 05/23/2006
• Est. Priority Date: 10/01/2004
• Status: Active Grant

• Current Assignee: Smiths Aerospace, LLC (GE Aerospace)
• Original Assignee: Smiths Aerospace, LLC (GE Aerospace)
• Inventors: Neis, Samuel C., Runals, Andrew W.
• Primary Examiner(s): Williams, Howard L.
• Application Number:
  US10/954,485
• Publication Number:
  US 20060071838A1
• Time in Patent Office: 599 Days
• Field of Search: 341/120, 341/139
• US Class Current: 341/139
• CPC Class Codes: H03F 1/34 Negative-feedback-circuit arrangements with or without positive feedback H03F1/02 - H03F1/30, H03F1/38 - H03F1/50, H03F3/50 take precedence ; for rejection of common mode signals H03F3/45479
• CPC Class Codes: H03F 2203/45138 Two or more differential amplifiers in IC-block form are combined, e.g. measuring amplifiers
• CPC Class Codes: H03F 2203/45572 the IC comprising one or more Zener diodes to the input leads
• CPC Class Codes: H03F 2203/45616 the IC comprising more than one switch, which are not cross coupled
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit
• CPC Class Codes: H03G 1/0088 using discontinuously variable devices, e.g. switch-operated
• CPC Class Codes: H03M 1/129 Means for adapting the input signal to the range the converter can handle, e.g. limiting, pre-scaling H03M1/18 takes precedence; Out-of-range indication

Abstract

An analog input front end includes a configurable gain stage and an analog-to-digital converter. The configurable gain stage receives an analog input signal, such as a differential analog input signal, and provides a gain value to the analog input signal so as to output a gain-adjusted analog input signal that is within a particular voltage range between a maximum and a minimum value. The analog-to-digital converter receives the gain-adjusted analog input signal and performs analog-to-digital conversion on the gain-adjusted analog input signal, so as to output a digital signal that is indicative of the analog input signal.

Claims

1. An analog input front end, comprising:

a configurable gain stage that is configured to receive an analog input signal and to provide a gain value to the analog input signal so as to output a gain-adjusted analog input signal that is within a particular voltage range between a maximum and a minimum value; and

an analog-to-digital converter that is configured to receive the gain-adjusted analog input signal output from the configurable gain stage, and to perform analog-to-digital conversion on the gain-adjusted analog input signal, so as to output a digital signal that is indicative of the analog input signal,

wherein the configurable gain stage comprises;

a positive differential input signal stage including a first operational amplifier; and

a negative differential input signal stage including a second operational amplifier,

wherein the positive differential input signal stage further comprises;

a first resistor and a first capacitor connected across the first operational amplifier and acting as a first frequency filter, and

wherein the negative differential input signal stage further comprises;

a second resistor and a second capacitor connected across the second operational amplifier and acting as a second frequency filter.

2. The analog input front end according to claim 1, wherein the positive differential input signal stage further comprises:

a first switch and a second switch capable of being switched so as to cause the positive differential gain stage to operate in an attenuation mode, a unity gain mode, and in a greater-than-unity gain mode; and

wherein the negative differential input signal stage further comprises;

a third switch and a fourth switch capable of being switched so as to cause the negative differential gain stage to operate in the attenuation mode and the unity gain mode, and in the greater-than-unity gain mode.

3. The analog input front end according to claim 2, further comprising:

a fifth switch provided between an output of the first operational amplifier of the positive differential gain stage and an input of the second operational amplifier of the negative differential gain stage.

4. A configurable gain stage, comprising:

a positive differential input signal stage that includes a first resistor having a first resistance value, a second resistor having a second resistance value, and a first operational amplifier; and

a negative differential input signal stage that includes a third resistor having the first resistance value, a fourth resistor having the second resistance value, and a second operational amplifier; and

first through sixth switches, the first and second switches being provided on the positive differential input signal stage, the third and fourth switches being provided on the negative differential input signal stage, the fifth switch being provided between the positive and negative differential input signal stages, and the sixth switch being provided between a ground potential and at least one of the positive and negative differential input signal stages,

wherein the configurable gain stage is capable of operating in a first mode of operation providing a gain value greater than unity to an input differential signal pair, a second mode of operation providing a unity gain value to the input differential signal pair, and a third mode of operation provide a gain value greater than zero but less than unity to the input differential signal pair.

5. The configurable gain stage according to claim 4, wherein the configurable gain stage includes means for providing an impedance buffer for signals to be processed by another device coupled at an output end of the configurable gain stage.

6. The configurable gain stage according to claim 4, wherein the configurable gain stage is coupled to an A/D converter, to act as both an impedance buffer and a dynamic range controller for signals to be processed by the A/D converter.

7. The configurable gain stage according to claim 4, further comprising:

a calibration control unit configured to control the configurable gain stage such that a maximum gain error of the configurable gain stage is less than a predetermined value for all operating states of the configurable gain stage.

8. The configurable gain stage according to claim 7, wherein the calibration control unit comprises:

an operational amplifier;

a resistor ladder circuit connected to the operational amplifier;

a digital-to-analog converter connected to the operational amplifier and to the resistor ladder;

a switch; and

a voltage reference unit connected to the resistor ladder by way of the switch, the voltage reference unit also being connected to the digital-to-analog converter.

9. A calibration circuit for a gain stage and analog-to-digital converter unit, the calibration circuit comprising:

an operational amplifier;

a digital-to-analog converter;

a resistor ladder provided between the operational amplifier and the digital-to-analog converter;

a voltage reference unit connected to the digital-to-analog converter; and

a plurality of switches that provide an on/off connection to the gain stage and the analog-to-digital converter unit,

wherein the calibration circuit is configured to maintain a total error of the gain stage and the analog-to-digital converter unit to be less than a predetermined value, for all operating modes of the gain stage and the analog-to-digital converter.

10. The calibration circuit according to claim 9, further comprising:

a resistor provided between an input port and an output port of the operational amplifier.

11. The calibration circuit according to claim 10, wherein the resistor has a predetermined resistance value with respect to a plurality of resistors making up the resistor ladder.

12. The calibration circuit according to claim 9, wherein the digital-to-analog converter is configured to receive digital data, as calibration instructions, for the calibration circuit.

13. The calibration circuit according to claim 9, further comprising:

a switch provided between at least one resistor of the resistor ladder and the voltage reference unit.