Phase change memory device

• US 7,050,328 B2
• Filed: 02/18/2004
• Issued: 05/23/2006
• Est. Priority Date: 12/27/2001
• Status: Expired due to Term

• Current Assignee: Ovonyx Memory Technology, LLC (Micron Technology, Inc.), STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: Ovonyx Incorporated (Micron Technology, Inc.), STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Khouri, Osama, Resta, Claudio
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Luu, Pho M.
• Application Number:
  US10/782,737
• Publication Number:
  US 20040228163A1
• Time in Patent Office: 825 Days
• Field of Search: 365/163, 365/154
• US Class Current: 365/163
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0038 Power supply circuits
• CPC Class Codes: G11C 13/0064 Verifying circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0054 Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor

Abstract

A phase change memory has an array formed by a plurality of cells, each including a memory element of calcogenic material and a selection element connected in series to the memory element; a plurality of address lines connected to the cells; a write stage and a reading stage connected to the array. The write stage is formed by current generators, which supply preset currents to the selected cells so as to modify the resistance of the memory element. Reading takes place in voltage, by appropriately biasing the selected cell and comparing the current flowing therein with a reference value.

Claims

1. A phase change memory device, comprising:

a memory array formed by a plurality of memory cells, each memory cell comprising a memory element of calcogenic material and a selection element connected in series to said memory element;

a plurality of address lines connected to said memory cells; and

a write stage connected to said memory array, said write stage including current generator means selectively connected to said address lines and supplying selected memory cells with currents having values that modify an electrical property of the memory element of said selected memory cells.

2. The memory device according to claim 1 wherein said write stage comprises a single current generator that is connected to said address lines.

3. The memory device according to claim 1 wherein said write stage comprises a plurality of current generator circuits, one for each selected address line connected to an addressed memory cell.

4. The memory device according to claim 3 wherein each current generator circuit comprises:

a plurality of generator transistors each having a control terminal receiving a respective control signal and an output terminal;

a load circuit having an input connected to said outpcut terminals of said generator transistors and an output connected to a respective selected address line; and

a logic circuit having a data input receiving a data signal and a plurality of outputs connected respectively to the control terminals of said generator transistors and generating said control signals according to said data signal.

5. The memory device according to claim 3 wherein each current generator circuit comprises:

a generator transistor having a control terminal receiving a control signal and an output terminal;

a load circuit having an input connected to said output terminal of said generator transistor and an output connected to a respective selected address line; and

a logic circuit having a data input receiving a data signal and an output connected to said control terminal of said generator transistor and generating said control signal of value correlated to said data signal.

6. The memory device according to claim 1, further comprising a read stage connected to said memory array, said read stage comprising:

voltage generator means connected to selected address lines for biasing said selected address lines at a preset read voltage and causing cell currents to flow in selected memory cells; and

comparator means connected to said selected address lines and comparing said cell currents with reference currents of preset value.

7. The memory device according to claim 6, further comprising an operation selector stage connected to said read stage, write stage and memory array for selectively connecting said selected address lines to said write stage and comparator means of said reading stage.

8. The memory device according to claim 6 wherein said comparator means comprise a dual-input dynamics differential circuit.

9. The memory device according to claim 6 wherein said comparator means comprise, for each selected address line:

a first subtractor element connected to a respective one of said selected address lines and to a reference line and generating an output voltage proportional to the difference between a cell current flowing in said respective selected address line and a reference current flowing in said reference line;

a second subtractor element connected to said respective selected address line and to said reference line and generating an output voltage proportional to the difference between said reference current and said flowing cell current, and

a differential amplifier connected to said first and to said second subtractor elements.

10. The memory device according to claim 9 wherein said comparator means further comprise:

a cell mirror circuit having an input connected to said respective address line;

a first and a second output supplying a current correlated to said cell current, said first output of said cell mirror circuit being connected to said first subtractor element;

a reference current mirror circuit having an input connected to said reference line;

a first and a second output supplying a current correlated to said reference current, said first output of said reference mirror circuit being connected to said second subtractor element;

a first mirror circuit connected between said second output of said cell mirror circuit and said second subtractor element; and

a second mirror circuit connected between said second output of said reference mirror circuit and said first subtractor element.

11. A phase change memory device, comprising:

a memory array formed by rows and columns of memory cells, each memory cell comprising a memory element of calcogenic material and a selection element connected in series to the memory element;

a plurality of bit lines connected respectively to the columns of memory cells; and

a write stage connected to the memory array, the write stage including a current generator selectively connected to a selected one of the bit lines and supplying a selected one of the memory cells connected to the selected bit line with a current having a value that modifies an electrical property of the selected memory cell, the current generator being structured to ensure that the value of the current does not depend on a position of the selected memory cell within the column to which the selected bit line is connected.

12. The memory device according to claim 11 wherein the current generator is connected to a plurality of the bit lines.

13. The memory device according to claim 11 wherein the write stage comprises a plurality of current generator circuits, one for each of the bit lines.

14. The memory device according to claim 11 wherein the current generator comprises:

a plurality of generator transistors each having a control terminal receiving a respective control signal and an output terminal;

a load circuit having an input connected to the output terminals of the generator transistors and an output connected to the selected bit line; and

a logic circuit having a data input receiving a data signal and a plurality of outputs connected respectively to the control terminals of the generator transistors and generating the control signals according to the data signal.

15. The memory device according to claim 11 wherein the current generator comprises:

a generator transistor having a control terminal receiving a control signal and an output terminal;

a load circuit having an input connected to the output terminal of the generator transistor and an output connected to a the selected bit line; and

a logic circuit having a data input receiving a data signal and an output connected to the control terminal of the generator transistor and generating the control signal of value correlated to the data signal.

16. The memory device according to claim 11, further comprising a read stage connected to the memory array, the read stage comprising:

a voltage generator connected to the selected bit line for biasing the selected bit line at a preset read voltage and causing a cell current to flow in the selected memory cell; and

a comparator connected to the selected bit line and structured to compare the cell current with a reference current of preset value.

17. The memory device according to claim 16 wherein the comparator comprises a dual-input dynamics differential circuit.

18. The memory device according to claim 16 wherein the comparator comprises:

a first subtractor element connected to the selected bit line and to a reference line and generating an output voltage proportional to the difference between a cell current flowing in the selected bit line and a reference current flowing in the reference line;

a second subtractor element connected to the selected bit line and to the reference line and generating an output voltage proportional to the difference between the reference current and the flowing cell current, and

a differential amplifier connected to the first and to the second subtractor elements.

19. The memory device according to claim 18 wherein the comparator further comprises:

a cell mirror circuit having an input connected to the select bit line;

a first and a second output supplying a current correlated to the cell current, the first output of the cell mirror circuit being connected to the first subtractor element;

a reference current mirror circuit having an input connected to the reference line;

a first and a second output supplying a current correlated to the reference current, the first output of the reference mirror circuit being connected to the second subtractor element;

a first mirror circuit connected between the second output of the cell mirror circuit and the second subtractor element; and

a second mirror circuit connected between the second output of the reference mirror circuit and the first subtractor element.

20. A phase change memory device, comprising:

a memory array formed by rows and columns of memory cells, each memory cell comprising a memory element of calcogenic material;

a plurality of bit lines connected respectively to the columns of memory cells; and

a current generator selectively connected to a selected one of the bit lines and supplying a selected one of the memory cells connected to the selected bit line with a current having a value that modifies an electrical property of the selected memory cell, the current generator being structured to provide a voltage to the selected memory cell that depends on a position of the selected memory cell within the column to which the selected bit line is connected.

21. The memory device according to claim 20 wherein the current generator is connected to a plurality of the bit lines.

22. The memory device according to claim 20 wherein the write stage comprises a plurality of current generator circuits, one for each of the bit lines.

23. The memory device according to claim 20 wherein the current generator comprises:

a plurality of generator transistors each having a control terminal receiving a respective control signal and an output terminal;

a load circuit having an input connected to the output terminals of the generator transistors and an output connected to the selected bit line; and

a logic circuit having a data input receiving a data signal and a plurality of outputs connected respectively to the control terminals of the generator transistors and generating the control signals according to the data signal.

24. The memory device according to claim 20, further comprising a read stage connected to the memory array, the read stage comprising:

a voltage generator connected to the selected bit line for biasing the selected bit line at a preset read voltage and causing a cell current to flow in the selected memory cell; and

a comparator connected to the selected bit line and structured to compare the cell current with a reference current of preset value.

25. The memory device according to claim 24 wherein the comparator comprises:

a first subtractor element connected to the selected bit line and to a reference line and generating an output voltage proportional to the difference between a cell current flowing in the selected bit line and a reference current flowing in the reference line;

a second subtractor element connected to the selected bit line and to the reference line and generating an output voltage proportional to the difference between the reference current and the flowing cell current, and

a differential amplifier connected to the first and to the second subtractor elements.