Digital-to-phase-converter

• US 7,050,467 B1
• Filed: 08/07/2000
• Issued: 05/23/2006
• Est. Priority Date: 08/07/2000
• Status: Active Grant

• Current Assignee: Motorola Solutions, Inc.
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Martin, Frederick L.
• Primary Examiner(s): Nguyen, Steven
• Assistant Examiner(s): SHAND, ROBERTA A
• Application Number:
  US09/633,705
• Time in Patent Office: 2,115 Days
• Field of Search: 370/503, 370516-519, 327/2, 327/3, 327/7, 327/10, 327/141, 327/161, 327/162, 327/163, 327/231, 327/233, 327/234, 327/235, 327/261, 327/276, 327/277, 327/284
• US Class Current: 370/517
• CPC Class Codes: H03K 2005/00156 using opamps, comparators, voltage multipliers or other analog building blocks
• CPC Class Codes: H03K 2005/00286 Phase shifter, i.e. the delay between the output and input pulse is dependent on the frequency, and such that a phase difference is obtained independent of the frequency
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03K 5/135 by the use of time reference signals, e.g. clock signals
• CPC Class Codes: H03K 7/04 Position modulation, i.e. PPM
• CPC Class Codes: H03L 7/0812 and where no voltage or current controlled oscillator is used

Abstract

A digital-to-phase or digital-to-time-shift converter (100) includes a delay line (106), a multiplexor (108) and synchronization circuit (110). In the converter (100) the clock edges of a reference signal are shifted in response to the value of a multi-bit digital word, IN (104). The synchronization circuit (110) gates the output of the multiplexor (108) such that a pulse appears at the synchronization circuit'"'"'s (110) output port (114) only when the circuit is gated by a signal at input TRIG (112). The synchronization circuit (110) creates a time aperture for the multiplexor output.

Claims

1. A digital-to-phase converter, comprising:

a delay line having a plurality of delay taps;

a multiplexor coupled to the delay line, the multiplexor having a plurality (N) of input ports for receiving the plurality of delay taps and an output port for providing an output signal and an input port for receiving an n-bit binary word (IN);

a synchronization circuit having a first input port for receiving the output signal from the multiplexor and a second input port for receiving a trigger signal, the synchronization circuit further having an output port for providing an output signal only when the synchronization circuit is gated by the trigger signal (TRIG); and

a reference clock providing a reference signal (REF) to the delay line and the synchronization circuit, wherein the reference signal (REF) is a pulse train having rising and falling edges and the synchronization circuit forms an aperture region when IN<

=N/2 that begins on the first rising edge of the reference signal (REF) after the first rising edge of the trigger signal (TRIG) signal and remains active for a predetermined period thereafter.

2. A digital-to-phase converter as defined in claim 1, wherein the predetermined period that the aperture region formed by the synchronization circuit remains active is approximately 3/2 the period (Tref) of the reference signal (REF).

3. A digital-to-phase converter as defined in claim 1, wherein the synchronization circuit forms an aperture region when IN>

N/2 that begins on the first falling edge after the first rising edge of the reference signal (REF) after a trigger signal (TRIG) has occurred and the aperture region remains active for a predetermined period of time.

4. A digital-to-phase converter as defined in claim 3, wherein the predetermined period of time that the aperture remains active is for approximately 3/2 the period (Tref) of the reference signal.