Data transfer engine of a processor having a plurality of modules

• US 7,051,123 B1
• Filed: 11/10/2000
• Issued: 05/23/2006
• Est. Priority Date: 10/14/1998
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd., Equator Technologies, Inc. (Pixelworks Incorporated)
• Inventors: Baker, David, Thekkath, Radhika, O'Donnell, John, Basoglu, Christopher, Raman, Ashok, Nojiri, Toru, Mundkur, Yatin, Lee, Woobin, Gervasio, Gregorio, Rehm, Eric, Cutler, Benjamin
• Primary Examiner(s): Gaffin, Jeffrey
• Assistant Examiner(s): SORRELL, ERON J
• Application Number:
  US09/710,192
• Time in Patent Office: 2,020 Days
• Field of Search: 710/22, 710/26, 710/31, 710/33
• US Class Current: 710/22
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/30 with priority control

Abstract

In an information processing system which has plurality of modules including a processor, a main memory and a plurality of I/O devices, a data transfer switch for performing data transfer operations between the processor, main memory and I/O devices comprises a request bus which has a request bus arbiter for receiving read and write requests from each one of the plurality of modules. A processor memory bus is configured to receive address and data information from a predetermined number of modules, including the processor. The processor memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules which are coupled to the processor memory bus.

An internal memory bus is configured to receive address and data information from a predetermined number of modules, including the memory and the I/O devices. The internal memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules coupled to the internal memory bus. A transceiver system is coupled to the processor memory bus and the internal memory bus for transferring data between the processor memory bus and the internal memory bus.

Claims

1. In an information processing system, having a plurality of modules including a processor, a cache memory, a main memory and a plurality of I/O devices, a data streamer for performing data transfer operations between said modules comprises:

a channel state memory configured to store a first allocated channel information, including data addresses, corresponding to a data transfer operation from a source module to said data streamer, and further configured to store a second allocated channel information, including data addresses, corresponding to said data transfer operation from said data streamer to a destination module;

a buffer memory allocated to said data transfer operation for receiving data provided by said source module in accordance with said first allocated channel information and providing said received data to said destination module in accordance with said second allocated channel information; and

a buffer state memory configured to store a relationship which determines that said first channel information and said second channel information and said buffer memory is used in said data transfer operation.

2. The data streamer in accordance with claim 1 wherein said channel state memory stores information corresponding to a plurality of data transfer operations between said modules.

3. The data streamer in accordance with claim 1, wherein a buffer memory is allocated for each one of said data transfer operations and the size of said buffer memory variably changes in accordance with the size of data in a corresponding data transfer operation.

4. The data streamer in accordance with claim 3 wherein the data transfer rate from a source module to a corresponding buffer in said buffer memory, is different than the data transfer rate from said buffer memory to a destination module.

5. The data streamer in accordance with claim 4 wherein said first allocated channel information includes a first channel descriptor, wherein said data transfer operation from a source module to said buffer is accomplished in accordance with said first channel descriptor.

6. The data streamer in accordance with claim 5, wherein said second allocated channel information includes a second channel descriptor, wherein said data transfer operation from said buffer to said destination module is accomplished in accordance with said second channel descriptor.

7. The data streamer in accordance with claim 1 wherein said data transfer operation from a source module to a destination module includes a data cache operation having a coherent allocation policy.

8. The data streamer in accordance with claim 1 wherein said data transfer operation from a source module to a destination module includes a data cache operation having a coherent no-allocation policy.

9. The data streamer in accordance with claim 1 wherein said data transfer operation from a source module to a destination module includes a data cache operation having a non-coherent no-allocation policy.

10. In an information processing system, having a plurality of modules including a processor, a cache memory, a main memory and a plurality of I/O devices, a data streamer for performing data transfer operations between said modules comprises:

a channel state memory configured to store a first allocated channel information including a first channel descriptor, wherein said data transfer operation from a source module to said buffer is accomplished in accordance with said first channel descriptor, said first channel information corresponding to a data transfer operation from a source module to said data streamer, and further configured to store a second allocated channel information, including a second channel descriptor, wherein said data transfer operation from said buffer to said destination module is accomplished in accordance with said second channel descriptor, said second channel information corresponding to said data transfer operation from said data streamer to a destination module, said first and said second channel descriptors having a different format and wherein the data transfer rate from a source module to a corresponding buffer in said buffer memory, is different than the data transfer rate from said buffer memory to a destination module; and

a buffer memory allocated to each one of said data transfer operation for receiving data provided by said source module in accordance with said first allocated channel information and providing said received data to said destination module in accordance with said second allocated channel information, and wherein the size of said buffet memory variably changes in accordance with the size of data in a corresponding data transfer operation.

11. In an information processing system, having a plurality of modules including a processor, a cache memory, a main memory and a plurality of I/O devices, a method for performing data transfer operations between said modules comprising the steps of:

storing a first allocated channel information, including data addresses, corresponding to a data transfer operation from a source module to a buffer memory;

storing a second allocated channel information, including data addresses, corresponding to said data transfer operation from said buffer memory to a destination module;

receiving data provided by said source module in accordance with said first allocated channel information;

providing said received data to said destination module in accordance with said second allocated channel information; and

storing a relationship in a buffer state memory which determines that said first channel information and said second channel information and said buffer memory is used in said data transfer operation.

12. The method in accordance with claim 11 further comprising the step of storing a plurality of said channel information each of which corresponding to a data transfer operation.

13. The method in accordance with claim 12, further comprising the step of allocating a buffer memory space within said buffer memory, and changing the size of said buffer memory space in accordance with the size of data in a corresponding data transfer operation.

14. The method in accordance with claim 13 further comprising the step of setting the data transfer rate from a source module to a corresponding buffer memory space at a different rate than the data transfer rate from said buffer memory space to a destination module.

15. The method in accordance with claim 14, further comprising the step of transferring data in accordance with a predetermined channel descriptor.

16. The method in accordance with claim 15 data streamer in accordance with claim 14 wherein said data transfer operation from a source module to a destination module includes a data cache operation having a coherent allocation policy.

17. The data streamer in accordance with claim 11 further comprising the step of providing data transfers having a data cache operation with a coherent no-allocation policy.

18. The data streamer in accordance with claim 11 further comprising the step of providing data transfers having a data cache operation with a non-coherent no-allocation policy.

19. In an information processing system, having a plurality of modules including a processor, a cache memory, a main memory and a plurality of I/O devices, a method for performing data transfer operations between said modules comprising the steps of:

storing a first allocated channel information, including a first channel descriptor, wherein said data transfer operation from a source module to said buffer is accomplished in accordance with said first channel descriptor, said first channel information corresponding to a data transfer operation from a source module to a buffer memory;

storing a second allocated channel information, including a second channel descriptor, wherein said darn transfer operation from said buffer to said destination module is accomplished in accordance with said second channel descriptor, said second channel information corresponding to said data transfer operation from said buffer memory to a destination module, said first and said second channel descriptors having a different format;

receiving data provided by said source module in accordance with said first allocated channel information; and

providing said received data to said destination module in accordance with said second allocated channel information, wherein the data transfer rate from a source module to a corresponding buffer in said buffer memory, is different than the data transfer rate from said buffer memory to a destination module and wherein the size of said buffer memory variably changes in accordance with the size of data in a corresponding data transfer operation.