Implementation of fast data processing with mixed-signal and purely digital 3D-flow processing boars
First Claim
1. A system, comprising:
- (a) at least one interfacing module for digitizing a multi-channel data stream into a plurality of multi-channel data sets, whereineach multi-channel data set in the plurality of multi-channel data sets represents a discrete time interval;
each multi-channel data set in the plurality of multi-channel data sets comprises a plurality of data signals;
said at least one interfacing module is configured to assign a time stamp to each data signal in each multi-channel data set; and
said at least one interfacing module is configured to determine a property, other than said time stamp, of each data signal in each multi-channel data set;
(b) a processor complex in electrical communication with said at least one interfacing module such that said processor complex receives ones of said multi-channel data sets in said plurality of multi-channel data sets from said at least one interfacing module at said discrete time interval, the processor complex comprising a plurality of channels, each channel in said plurality of channels adapted to receive one or more signals in said multi-channel data set, each channel comprising;
at least a first processor and a second processor;
whereinsaid first processor and said second processor each respectively have an input port and an output port;
said first processor is associated with a bypass switch and a bypass register, said bypass switch having (i) a first state that causes a signal in said multi-channel data set to bypass said first processor and be stored in said bypass register and (ii) a second state that causes a signal in said multi-channel data set to be input into said first processor; and
the input port of the second processor is adapted to receive data corresponding to one of said plurality of signals from the output port of the first processor; and
(c) at least one decision module adapted to receive and analyze processed data from all or a portion of the channels in said plurality of channels.
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Abstract
A system extends the execution time of a pipeline stage to a time longer than the time interval between two consecutive input data. Each processor in the system has an input and output port connected to a “bypass switch” (or multiplexer). Input data is sent either to a processor, for processing, or to a processor output port, in which case no processing is performed, through a register using at least one clock cycle to move data from register input to register output. For a single channel requiring an execution time twice the time interval between two consecutive input data, two processors are interconnected by the bypass switch. Data flows from the first processor at the input of the system, through the “bypass switches” of the interconnected processors, to output. The “bypass switches” are configured with respect to the processors such that the system data rate is independent of processor number.
60 Citations
21 Claims
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1. A system, comprising:
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(a) at least one interfacing module for digitizing a multi-channel data stream into a plurality of multi-channel data sets, wherein each multi-channel data set in the plurality of multi-channel data sets represents a discrete time interval; each multi-channel data set in the plurality of multi-channel data sets comprises a plurality of data signals; said at least one interfacing module is configured to assign a time stamp to each data signal in each multi-channel data set; and said at least one interfacing module is configured to determine a property, other than said time stamp, of each data signal in each multi-channel data set; (b) a processor complex in electrical communication with said at least one interfacing module such that said processor complex receives ones of said multi-channel data sets in said plurality of multi-channel data sets from said at least one interfacing module at said discrete time interval, the processor complex comprising a plurality of channels, each channel in said plurality of channels adapted to receive one or more signals in said multi-channel data set, each channel comprising; at least a first processor and a second processor;
whereinsaid first processor and said second processor each respectively have an input port and an output port; said first processor is associated with a bypass switch and a bypass register, said bypass switch having (i) a first state that causes a signal in said multi-channel data set to bypass said first processor and be stored in said bypass register and (ii) a second state that causes a signal in said multi-channel data set to be input into said first processor; and the input port of the second processor is adapted to receive data corresponding to one of said plurality of signals from the output port of the first processor; and (c) at least one decision module adapted to receive and analyze processed data from all or a portion of the channels in said plurality of channels. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. An apparatus for processing, in real-time, a multi-channel data set arriving at a data rate of tens of MHz or higher, and for providing a computational result within a few hundreds of nanoseconds from a time when the multi-channel data set arrived at said apparatus, the apparatus comprising:
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(a) at least one interfacing module for conditioning a plurality of received signals in said multi-channel data set, wherein each received signal in the plurality of received signals corresponds to a channel in said multi-channel data set; and
wherein the at least one interfacing module collectively comprises;instructions for assigning a time stamp to each received signal in said plurality of received signals, each said time stamp corresponding to a time when the corresponding received signal in the plurality of received signals was generated or detected; instructions for determining a property, other than a time stamp, of each received signal in the plurality of received signals; and instructions for converting the property and the time stamp for each received signal in the plurality of received signals to a corresponding digital signal, thereby forming a plurality of digital signals; (b) a plurality of processor channels, the plurality of processor channels arranged so that logical or actual neighboring processor channels represent digital signals derived from neighboring received signals in said multi-channel data set, the plurality of processor channels adapted to receive and process the plurality of digital signals, each processor channel in the plurality of processor channels comprising a processor having a capability of signal correlation between neighboring processor channels in said plurality of processor channels; and (c) at least one decision module adapted to receive and analyze processed data from each processor channel in said plurality of processor channels, the at least one decision module configured to analyze data from said plurality of processor channels based at least on said time-stamp and said property in each digital signal in said plurality of digital signals so that data from said plurality of processor channels can be correlated irrespective of whether such data was processed by neighboring processor channels in said plurality of processor channels to thereby determine whether a pattern of interest occurs in said data set. - View Dependent Claims (21)
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Specification