Upper-bound calculation for placed circuit design performance
First Claim
1. Within a computer automated tool, a method of estimating an upper-bound for an operational frequency of at least a portion of a placed circuit design comprising:
- (a) identifying a clock source within the placed circuit design, wherein the clock source is associated with a clock domain;
(b) determining an initial routing of connections of the clock domain;
(c) determining a minimum path slack corresponding to each connection of the clock domain;
(d) selecting the connections based on minimum path slack; and
(e) routing one or more of the selected connections in delay mode.
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Accused Products
Abstract
Within a computer automated tool, a method (400) of estimating an upper-bound of an operational frequency of at least a portion of a placed circuit design can include identifying (405) a clock source within the placed circuit design, wherein the clock source is associated with a clock domain, and determining (410) an initial routing of the clock domain. The method also can include determining (420) a minimum path slack corresponding to each connection of the clock domain. Connections of the clock domain which have a lowest minimum path slack can be marked (430). One or more marked connections which are not routed in delay mode can be identified and routed in delay mode (455) allowing sharing of routing resources by different nets.
15 Citations
34 Claims
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1. Within a computer automated tool, a method of estimating an upper-bound for an operational frequency of at least a portion of a placed circuit design comprising:
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(a) identifying a clock source within the placed circuit design, wherein the clock source is associated with a clock domain; (b) determining an initial routing of connections of the clock domain; (c) determining a minimum path slack corresponding to each connection of the clock domain; (d) selecting the connections based on minimum path slack; and (e) routing one or more of the selected connections in delay mode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. Within a computer automated tool, a method of estimating an upper-bound of an operational frequency of at least a portion of a placed circuit design comprising:
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(a) constraining at least two clock sources within the placed circuit design to a same target frequency, wherein each clock source is associated with a different clock domain; (b) determining an initial routing of connections of the clock domains; (c) determining a minimum path slack corresponding to each connection of the plurality of clock domains; (d) marking connections of the plurality of clock domains which have a lowest minimum path slack; (e) identifying marked connections which are not routed in delay mode; and (f) routing one or more of the identified connections in delay mode. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A machine readable storage, having stored thereon a computer program having a plurality of code sections executable by a machine for causing the machine to perform the steps of:
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(a) identifying a clock source within a placed circuit design, wherein the clock source is associated with a clock domain; (b) determining an initial routing of connections of the clock domain; (c) determining a minimum path slack corresponding to each connection of the clock domain; (d) marking connections of the clock domain which have a lowest minimum path slack; (e) identifying marked connections which are not routed in delay mode; and (f) routing one or more of the identified connections in delay mode. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23)
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24. A machine readable storage, having stored thereon a computer program having a plurality of code sections executable by a machine for causing the machine to perform the steps of:
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(a) constraining at least two clock sources within a placed circuit design to a same target frequency, wherein each clock source is associated with a different clock domain; (b) determining an initial routing of connections of the clock domains; (c) determining a minimum path slack corresponding to each connection of the plurality of clock domains; (d) marking connections of the plurality of clock domains which have a lowest minimum path slack; (e) identifying marked connections which are not routed in delay mode; and (f) routing one or more of the identified connections in delay mode. - View Dependent Claims (25, 26, 27, 28, 29, 30)
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31. A system configured to estimate an upper-bound of an operational frequency of at least a portion of a placed circuit design, comprising:
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(a) means for identifying a clock source within the placed circuit design, wherein the clock source is associated with a clock domain; (b) means for determining an initial routing of connections of the clock domain; (c) means for determining a minimum path slack corresponding to each connection of the clock domain; (d) means for marking connections of the clock domain which have a lowest minimum path slack; (e) means for identifying marked connections which are not routed in delay mode; (f) means for routing one or more of the identified connections in delay mode; and (g) means for repeating steps (c)–
(f) until all marked connections are routed in delay mode. - View Dependent Claims (32)
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33. A system configured to estimate an upper-bound of an operational frequency of at least a portion of a placed circuit design, comprising:
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(a) means for constraining at least two clock sources within the placed circuit design to a same target frequency, wherein each clock source is associated with a different clock domain; (b) means for determining an initial routing of connections of the clock domains; (c) means for determining a minimum path slack corresponding to each connection of the plurality of clock domains; (d) means for marking connections of the plurality of clock domains which have a lowest minimum path slack; (e) means for identifying marked connections which are not routed in delay mode; (f) means for routing one or more of the identified connections in delay mode; and (g) means for repeating steps (c)–
(f) until all marked connections are routed in delay mode. - View Dependent Claims (34)
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Specification