Method of forming trench transistor with chained implanted body including a plurality of implantation with different energies

• US 7,052,963 B2
• Filed: 01/28/2004
• Issued: 05/30/2006
• Est. Priority Date: 04/22/1999
• Status: Expired due to Term

• Current Assignee: Advanced Analogic Technologies Incorporated (Skyworks Solutions Incorporated)
• Original Assignee: Advanced Analogic Technologies Incorporated (Skyworks Solutions Incorporated)
• Inventors: Williams, Richard K., Grabowski, Wayne
• Primary Examiner(s): Brewster, William M.
• Application Number:
  US10/767,030
• Publication Number:
  US 20040191994A1
• Time in Patent Office: 853 Days
• Field of Search: 438/270, 438/272, 438/268, 438/514, 438/527, 438/432, 438/431, 438/433, 438/451, 438/589, 257/330, 257/329, 257/302, 257/328, 257/396
• US Class Current: 438/268
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A “chained implant” technique forms a body region in a trench gated transistor. In one embodiment, a succession of “chained” implants can be performed at the same dose but different energies. In other embodiments different doses and energies can be used, and particularly, more than one dose can be used in a single device. This process produces a uniform body doping concentration and a steeper concentration gradient (at the body-drain junction), with a higher total body charge for a given threshold voltage, thereby reducing the vulnerability of the device to punchthrough breakdown. Additionally, the source-body junction does not, to a first order, affect the threshold voltage of the device, as it does in DMOS devices formed with conventional diffused body processes.

Claims

1. A method of fabricating a MOSFET, comprising:

forming a trench in a surface of a semiconductor, the trench defining a mesa;

forming a first insulating layer along a wall of the trench;

forming a gate in the trench, the gate being insulated from the semiconductor by the insulating layer;

performing a plurality of implantations of dopant of a first conductivity type into the mesa to form a body region, wherein each of the implantations has a different energy, and each of the implantations is performed at a dose that is the same as the dose for another of the implantations; and

implanting dopant of a second conductivity type into the mesa to form a source region.

2. The method of claim 1, wherein the dose of the implantations is about 7·

10¹² cm<sup>−

2</sup>.

3. The method of claim 2, wherein the different energies respectively of the implantations comprise 1 MeV, 700 keV, 525 keV, 375 keV, 225 keV and 125 keV.

4. The method of claim 1, wherein forming the trench comprises:

forming a hard mask on the semiconductor; and

etching the semiconductor through an opening in the hard mask to form the trench.

5. The method of claim 4, wherein forming the gate comprises introducing polysilicon into the trench.

6. The method of claim 5, further comprising:

with the hard mask in place, oxidizing an exposed surface of the polysilicon to form a second oxide layer at the top of the trench, the second oxide layer extending down into the trench;

removing the hard mask; and

depositing a metal layer on a surface of the second oxide layer and the surface of the mesa.

7. The method of claim 1, further comprising:

forming a second insulating layer over the mesa;

etching an opening in the second insulating layer; and

depositing a metal layer into the contact opening to form an electrical contact with the source region.

8. A method of fabricating a MOSFET, comprising:

forming a trench in a surface of a semiconductor, the trench defining a mesa, wherein forming the trench comprises forming a hard mask on the semiconductor, and etching the semiconductor through an opening in the hard mask to form the trench;

forming a first insulating layer along a wall of the trench;

forming a gate in the trench, the gate being insulated from the semiconductor by the insulating layer;

performing a plurality of implantations of dopant of a first conductivity type into the mesa to form a body region, wherein each of the implantations has a different energy, and a maximum implant energy for the implantations causes dopant of the first conductivity type to penetrate through the hard mask into the semiconductor to a depth desired for a junction between the body region and a drain region; and

implanting dopant of a second conductivity type into the mesa to form a source region.

9. The method of claim 8, wherein a first of the implantations is at a first dose, and a second of the implantations is at a second dose, the second dose differing from the first dose.

10. The method of claim 8, wherein respective doses and energies of the implantations are such that the implantations in combination provide a uniform doping for the body region.

11. The method of claim 8, further comprising completing the MOSFET without performing a process to diffuse the dopant of the first conductivity type in the body region, whereby energies of the implantations control a depth of a body-drain junction at an interface between the body region and an underlying portion of the semiconductor.

12. The method of claim 8, further comprising:

removing the hard mask;

forming a second insulating layer over the mesa;

etching an opening in the second insulating layer; and

depositing a metal layer into the contact opening to form an electrical contact with the source region.

13. The method of claim 8, further comprising:

with the hard mask in place, oxidizing an exposed surface of the polysilicon to form a second oxide layer at the top of the trench, the second oxide layer extending down into the trench;

removing the hard mask; and

depositing a metal layer on a surface of the second oxide layer and the surface of the mesa.

14. A method of fabricating a MOSFET, comprising:

forming a trench in a surface of a semiconductor, the trench defining a mesa, wherein forming the trench comprises forming a hard mask on the semiconductor, and etching the semiconductor through an opening in the hard mask to form the trench;

forming a first insulating layer along a wall of the trench;

forming a gate in the trench, the gate being insulated from the semiconductor by the insulating layer, wherein forming the gate comprises introducing polysilicon into the trench;

performing a plurality of implantations of dopant of a first conductivity type into the mesa to form a body region, wherein each of the implantations has a different energy;

implanting dopant of a second conductivity type into the mesa to form a source region;

with the hard mask in place, oxidizing an exposed surface of the polysilicon to form a second oxide layer at the top of the trench, the second oxide layer extending down into the trench;

removing the hard mask; and

depositing a metal layer on a surface of the second oxide layer and the surface of the mesa.

15. The method of claim 14, wherein each of the implantations is performed at a dose that is the same as the dose for another of the implantations.

16. The method of claim 14, wherein a first of the implantations is at a first dose, and a second of the implantations is at a second dose, the second dose differing from the first dose.

17. The method of claim 14, wherein respective doses and energies of the imp lantations are such that the implantations in combination provide a uniform doping for the body region.

18. The method of claim 14, further comprising completing the MOSFET without performing a process to diffuse the dopant of the first conductivity type in the body region, whereby energies of the implantations control a depth of a body-drain junction at an interface between the body region and an underlying portion of the semiconductor.