Method of manufacturing a semiconductor device having selective epitaxial silicon layer on contact pads

• US 7,052,983 B2
• Filed: 10/16/2003
• Issued: 05/30/2006
• Est. Priority Date: 01/22/2003
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Ji-Young, Park, Byung-Jun
• Primary Examiner(s): Smith, Zandra V.
• Assistant Examiner(s): DUONG, KHANH B
• Application Number:
  US10/688,017
• Publication Number:
  US 20040149992A1
• Time in Patent Office: 957 Days
• Field of Search: 438/597, 438/607, 438/637, 438/675, 438/680, 438/684, 438/685
• US Class Current: 438/607
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 12/0335 Making a connection between the transistor and the capacitor, e.g. plug
• CPC Class Codes: H10B 12/315 with the capacitor higher than a bit line
• CPC Class Codes: H10B 12/485 Bit line contacts

Abstract

Wirings including first conductive layer patterns and insulating mask layer patterns are formed on a substrate. Insulating spacers are formed on sidewalls of the wirings. Self-aligned contact pads including portions of a second conductive layer are formed to contact with surfaces of the insulating spacers and to fill up a gap between the wirings. An interlayer dielectric layer is formed on the substrate where the contact pads are formed and is then partially etched to form contact holes exposing the contact pads. A selective epitaxial silicon layer is formed on the contact pads exposed through the contact holes to cover the insulating mask layer patterns. Thus, a short-circuit between the lower wiring and an upper wiring formed in the contact holes is prevented.

Claims

1. A method of manufacturing a semiconductor device comprising:

forming wirings separated from each other on a semiconductor substrate, each of the wirings including a first conductive layer pattern and an insulating mask layer pattern formed on the first conductive layer pattern;

forming insulating spacers on sidewalls of the wirings;

forming self-aligned contact pads including portions of a second conductive layer, each of the self-aligned contact pads making contact with surfaces of the insulating spacers to fill a gap between the wirings;

forming an interlayer dielectric layer on the substrate wherein the contact pads are formed;

partially etching the interlayer dielectric layer to form contact holes exposing the contact pads; and

forming a selective epitaxial silicon layer on the contact pads exposed through the contact holes to cover the insulating mask layer pattern.

2. The method of claim 1, wherein the insulating mask layer pattern and the insulating spacers comprise materials having etching selectivities relative to the interlayer dielectric layer.

3. The method of claim 2, wherein the insulating mask layer pattern and the insulating spacers comprise silicon nitride based materials.

4. The method of claim 1, wherein the second conductive layer comprises doped polysilicon.

5. A method of manufacturing a semiconductor device comprising:

forming wirings separated from each other on a semiconductor substrate, each of the wirings including a first conductive layer pattern and an insulating mask layer pattern formed on the first conductive layer pattern;

forming insulating spacers on sidewalls of the wirings;

forming at least two self-aligned contact pads using mask patterns having bar shapes that include openings having at least two different contact regions, each of the at least two self-aligned contact pads in contact with portions of the substrate between the wirings;

forming an interlayer dielectric layer on the substrate where the at least two self-aligned contact pads are formed;

partially etching the interlayer dielectric layer to form a contact hole exposing one of the at least two self-aligned contact pads; and

forming a selective epitaxial silicon layer on the one of the at least two self-aligned contact pads to cover the insulating mask layer pattern.

6. The method of claim 5, wherein the insulating mask layer pattern and the insulating spacers comprise materials having etching selectivities relative to the interlayer dielectric layer.

7. The method of claim 6, wherein the insulating mask layer pattern and the insulating spacers comprise silicon nitride based materials.

8. The method of claim 5, wherein forming at least two different contact pads comprises:

forming a first interlayer dielectric layer on the insulating spacers, the wirings, and the substrate;

etching the first interlayer dielectric layer using the insulating mask layer pattern until the portions of the substrate between the wirings are exposed;

forming a second conductive layer on the first interlayer dielectric layer and the portions of the substrate between the wirings; and

planarizing the second conductive layer and the first interlayer dielectric layer until a surface of the insulating mask layer pattern is exposed.

9. The method of claim 8, wherein planarizing the second conductive layer and the first interlayer dielectric layer is performed using a process selected from the group consisting of a CMP process, an etch-back process, and a combination of the CMP and etch-back processes.

10. The method of claim 5, wherein the contact hole is formed to have a line shape so that the one of the at least two self-aligned contact pads and another self-aligned contact pad arranged in a direction substantially parallel to the wirings are simultaneously exposed through the contact hole.

11. The method of claim 5, further comprising:

after forming the selective epitaxial silicon layer, forming contact spacers on inner sidewalls of the contact holes using the selective epitaxial silicon layer as an etching stopper; and

forming a third conductive layer in the contact hole that is electrically connected to the one of the at least two self-aligned contact pads.

12. The method of claim 11, wherein the contact spacers comprise a material having an etching selectivity relative to the interlayer dielectric layer.

13. The method of claim 12, wherein the contact spacers comprise a silicon nitride based material.

14. The method of claim 5, wherein forming the wirings comprises forming the first conductive layer pattern in contact with an upper surface of the substrate and forming the insulating mask layer pattern in contact with an upper surface of the first conductive layer pattern.

15. The method of claim 5, wherein forming the selective epitaxial silicon layer on the one of the at least two self-aligned contact pads comprises forming the selective epitaxial silicon layer in contact with an upper surface of the one of the at least two self-aligned contact pads.

16. The method of claim 15, wherein forming the selective epitaxial silicon layer on the one of the at least two self-aligned contact pads further comprises forming a layer consisting of silicon.

17. A method of manufacturing a semiconductor device comprising:

forming gate lines that cross active regions on a semiconductor substrate, wherein each of the gate lines includes a gate mask layer pattern and gate spacers formed on sidewalls of the gate mask layer pattern so that storage node contact regions and bit line contact regions are formed on portions of the substrate between the gate lines;

forming first contact pads connected to the storage node contact regions and second contact pads connected to the bit line contact regions using self-aligned contact mask patterns having bar shapes that include openings exposing the active regions;

forming an interlayer dielectric layer on the substrate where the first and second contact pads are formed;

partially etching the interlayer dielectric layer to form storage node contact holes having line shapes so that one first contact pad and an adjacent first contact pad arranged in a direction substantially parallel to the gate lines are exposed by each of the storage node contact holes;

forming a selective epitaxial silicon layer on the first contact pads exposed by the storage node contact holes to cover the gate mask layer patterns; and

forming storage node contact plugs in the storage node contact holes, wherein the storage node contact plugs are electrically connected to the first contact pads.

18. The method of claim 17, wherein the gate mask layer pattern and the gate spacers comprise silicon nitride based materials.

19. The method of claim 17, wherein forming first contact pads and second contact pads comprises:

forming a first interlayer dielectric layer on the gate lines and the substrate;

etching the first interlayer dielectric layer using the self-aligned contact mask patterns until the storage node contact regions and the bit line contact regions are exposed between the gate lines;

forming a first conductive layer on the first interlayer dielectric layer, the storage node contact regions, and the bit line contact regions; and

planarizing the first conductive layer and the first interlayer dielectric layer until the gate mask layer patterns are exposed.

20. The method of claim 19, wherein planarizing the first conductive layer and the first interlayer dielectric layer is performed using a process selected from the group consisting of a CMP process, an etch-back process, and a combination of the CMP and the etch-back processes.

21. The method of claim 17, further comprising, before forming the storage node contact plugs, forming contact spacers on inner sidewalls of the storage node contact holes using the selective epitaxial silicon layer as an etching stopper.

22. The method of claim 21, wherein the contact spacers comprise a silicon nitride based material.

23. The method of claim 17, wherein forming storage node contact plugs comprises:

forming a second conductive layer on the interlayer dielectric layer to fill the storage node contact holes; and

planarizing the second conductive layer until a surface of the interlayer dielectric layer is exposed, thereby separating the storage node contact plugs into node units.

24. The method of claim 17, further comprising:

before forming the interlayer dielectric layer, forming a second interlayer dielectric layer on the substrate where the first and second contact pads are formed;

partially etching the second interlayer dielectric layer to form bit line contact holes exposing the second contact pads on the bit line contact regions;

forming a first selective epitaxial silicon layer on the second contact pads exposed through the bit line contact holes to cover the gate mask layer patterns; and

forming bit lines on the second interlayer dielectric layer to fill the bit line contact holes, wherein the bit lines are electrically connected to the second contact pads through the bit line contact holes.