Semiconductor integrated circuit including an inductor and method of manufacturing the same

• US 7,053,165 B2
• Filed: 06/20/2003
• Issued: 05/30/2006
• Est. Priority Date: 06/24/2002
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Furumiya, Masayuki, Yamamoto, Ryota
• Primary Examiner(s): Tran, Minhloan
• Assistant Examiner(s): TRAN, TAN N
• Application Number:
  US10/600,104
• Publication Number:
  US 20040004266A1
• Time in Patent Office: 1,075 Days
• Field of Search: 257/531, 257/295, 257/425, 257/427, 257/528
• US Class Current: 257/531
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 27/34 Special means for preventing or reducing unwanted electric or magnetic effects, e.g. no-load losses, reactive currents, harmonics, oscillations, leakage fields
• CPC Class Codes: H01F 41/046 structurally combined with ferromagnetic material
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor integrated circuit device, and method of manufacturing the same, includes an inductor with improved inductance and an improved quality factor (Q-factor) that can be miniaturized. In one example, an inductor (3) is provided on an insulating layer (2) of a multilayer interconnection layer (1). The inductor (3) is formed by a spiral arrangement of a wiring (3a). A lamination film (14) is provided in an internal region (13) of an inductor (3) on insulating layer (2), and can be formed by laminating a titanium-tungsten (TiW) layer (9), a copper (Cu) layer (10), a ferromagnetic substance layer (15) made of nickel (Ni), a Cu layer (11), and a TiW layer (12), in that order. A lower surface of ferromagnetic substance layer (15) can be lower than an upper surface of wiring layer (3a), and an upper surface of ferromagnetic substance layer (15) can be higher than a lower surface of wiring layer (3a). As a result, a lower portion of ferromagnetic substance layer (15) can be at the same layer (level) as wiring layer (3a). An upper surface of lamination film (14) can be made higher than a wiring layer (3a), and a lower surface of lamination film (14) can be made lower than a lower surface of a wiring layer (3a).

Claims

1. A semiconductor integrated circuit, comprising:

an inductor on a substrate;

a first metal layer inside the inductor when viewed from a direction perpendicular to a surface of the substrate, a lower surface of the first metal layer being no higher than a lower surface of the inductor;

a ferromagnetic substance layer on the first metal layer, a lower surface of the ferromagnetic substance layer being lower than an upper surface of the inductor, an upper surface of the ferromagnetic substance layer being higher than the lower surface of the inductor; and

a second metal layer that covers an upper and side surface of the ferromagnetic substance layer, an upper surface of the second metal layer being no lower than the upper surface of the inductor.

2. The semiconductor integrated circuit of claim 1, wherein:

the ferromagnetic substance layer is divided into a plurality of parts that are separate from one another when viewed from the direction perpendicular to a surface of the substrate.

3. The semiconductor integrated circuit of claim 1, further including:

a multilayer interconnection layer on the substrate; and

the inductor and a laminated film are formed on an uppermost layer of the multilayer interconnection layer, the laminated film comprising the first metal layer, the ferromagnetic substance layer, and the second metal layer.

4. The semiconductor integrated circuit of claim 1, wherein:

the inductor, first metal layer and second metal layer comprise a metal selected from the group consisting of copper and aluminum.

5. The semiconductor integrated circuit of claim 1, wherein:

the ferromagnetic substance layer comprises nickel.

6. A semiconductor integrated circuit, comprising:

an inductor on a substrate; and

a laminated film beside the inductor wherein

the laminated film having a ferromagnetic substance layer and a metal layer covering the ferromagnetic substance layer to prevent diffusion of the ferromagnetic substance layer.

7. The semiconductor integrated circuit of claim 6, wherein:

the laminated film formed inside the inductor when viewed from a direction perpendicular to a surface of the substrate.

8. The semiconductor integrated circuit of claim 7, wherein:

the ferromagnetic substance layer is divided into a plurality of parts separated from one another when viewed from a direction perpendicular to a surface of the substrate.

9. The semiconductor integrated circuit of claim 6, wherein:

the laminated film is free from overlapping the inductor and surrounds the inductor when viewed from a direction perpendicular to a surface of the substrate.

10. The semiconductor integrated circuit of claim 6, furthering including:

a multilayer interconnection layer on the substrate wherein the inductor and the laminated film are formed in different layers of the multilayer interconnection layer from each other.

11. The semiconductor integrated circuit of claim 10, wherein:

the laminated film is divided into a plurality of parts separated from one another; and

the parts are arranged in a radial fashion around a center area of the inductor.

12. The semiconductor integrated circuit of claim 11, wherein:

each of the parts has a strip-like shape and is disposed longitudinally in a direction from the center area of the inductor toward a periphery of the inductor.

13. The semiconductor integrated circuit of claim 10, further including:

a pad formed in a same layer as the laminated film.

14. The semiconductor integrated circuit of claim 13, wherein:

the pad has the same laminated structure as the laminated film.

15. The semiconductor integrated circuit of claim 10, wherein:

the laminated film covers essentially all of the inductor when viewed from a direction perpendicular to a surface of the substrate.

16. A semiconductor integrated circuit comprising:

an inductor on a substrate;

a laminated film beside the inductor wherein

the laminated film having a ferromagnetic substance layer and a metal layer covering the ferromagnetic substance layer to prevent diffusion of the ferromagnetic substance layer; and

the metal layer having a first layer and a second layer; and

a lower surface of the ferromagnetic substance layer is covered with the first layer and an upper surface and a side surface of the ferromagnetic substance layer is covered with the second layer.

17. The semiconductor integrated circuit of claim 16, wherein:

the inductor having a laminated structure of the first layer and the second layer.

18. The semiconductor integrated circuit of claim 16, wherein:

each of the first layer and the second layer includes a barrier metal layer.

19. A semiconductor integrated circuit comprising:

an inductor on a substrate;

a laminated film beside the inductor wherein

the laminated film having a ferromagnetic substance layer and a metal layer covering the ferromagnetic substance layer to prevent diffusion of the ferromagnetic substance layer; and

the metal layer includes a barrier metal layer.

20. A semiconductor integrated circuit comprising:

an inductor on a substrate;

a laminated film beside the inductor wherein

the laminated film having a ferromagnetic substance layer and a metal layer covering the ferromagnetic substance layer to prevent diffusion of the ferromagnetic substance layer; and

a multilayer interconnection layer on the substrate wherein the inductor and the laminated film are formed on an uppermost layer of the multilayer interconnection layer.