Optimized channel controller for NMR apparatus

• US 7,053,614 B2
• Filed: 04/08/2004
• Issued: 05/30/2006
• Est. Priority Date: 04/08/2004
• Status: Expired due to Fees

• Current Assignee: Agilent Technologies, Inc.
• Original Assignee: Varian Incorporated (Agilent Technologies, Inc.)
• Inventors: Hornung, Phillip A.
• Primary Examiner(s): ARANA, LOUIS M
• Application Number:
  US10/820,621
• Publication Number:
  US 20050225325A1
• Time in Patent Office: 782 Days
• Field of Search: 324/312, 324/300, 324/322, 324/318
• US Class Current: 324/312
• CPC Class Codes: G01R 33/3607 RF waveform generators, e.g. frequency generators, amplitude-, frequency- or phase modulators or shifters, pulse programmers, digital to analog converters for the RF signal, means for filtering or attenuating of the RF signal
• CPC Class Codes: G01R 33/54 Signal processing systems, e.g. using pulse sequences ; Generation or control of pulse sequences; Operator console
• CPC Class Codes: G01R 33/543 Control of the operation of the MR system, e.g. setting of acquisition parameters prior to or during MR data acquisition, dynamic shimming, use of one or more scout images for scan plane prescription G01R33/546 takes precedence

Abstract

A controller for apparatus assuming a sequence of precisely synchronized states in accordance with a lengthy event stream is realized in an architecture comprising a register layer comprising a plurality of latched registers for receiving event descriptors and parameters from a bus and a computational/logical layer for operations on/among certain of said parameters for presentation to external operational devices. An RF controller controlling frequency, pulse width, amplitude with precise timing for magnetic resonance applications is one example and a magnetic gradient controller controlling vector magnitude and orientation is another.

Claims

1. A controller for producing a sequence of states derived from an input bus, each said state comprising a plurality of independent variables realized as digital values, each said variable expressed in a corresponding digital precision and said state further characterized by duration, said controller comprising,

(a) a plurality of latched registers for receiving and retaining corresponding datums from said input bus,

(b) at least one latched mathematical register assembly for receiving and retaining corresponding datums from said input bus, said latched mathematical register assembly comprising a computational module for combining said datums in accord with a mathematical rule to yield a computed result datum, and a corresponding latched result register to retain said computed result datum, and

(c) a plurality of FIFO portions, each portion in correspondence with one said latched register and latched result register, each said latched register and result register in corresponding relationship with one said FIFO portion, whereby a FIFO assembly comprising said FIFO portions contains a sequence of said states.

2. The controller of claim 1, wherein said FIFO assembly comprises an output register and wherein a duration interval is derived from each said state, each said state persisting in said output register for said duration interval.

3. The controller of claim 1, wherein said state comprises a vector field.

4. The controller of claim 3, wherein said vector is a magnetic gradient.

5. The controller of claim 3, wherein said vector is a magnetic gradient.

6. The controller of claim 1, wherein said state comprises an RF field.

7. The controller of claim 1, wherein said state comprises a vector field.

8. The controller of claim 1, wherein said state comprises an RF field.

9. A controller for producing a sequence of states derived from an input bus, each said state comprising a plurality of independent variables realized as digital values, each said variable expressed in a corresponding digital precision and said state further characterized by duration, said controller comprising,

(a) a plurality of latched registers for receiving and retaining corresponding datums from said input bus and wherein at least one said latched register comprises an argument portion of said datum, an increment portion of said datum and an adder for modifying said argument through addition of said increment portion and communication of the result thereof both to a corresponding mathematical register and to replace the value held in said argument portion of said at least one latched register,

(b) at least one latched mathematical register array for receiving and retaining corresponding datums from said corresponding latched register, said latched mathematical register array comprising a computational module for combining said datums in accord with a mathematical rule to yield a computed result datum, and the corresponding latched mathematical register adapted to retain said computed result datum, and

(c) a plurality of FIFO portions, each portion in correspondence with one said latched register and latched mathematical register, each said latched register and latched mathematical register in corresponding relationship with one said FIFO portion, whereby a FIFO assembly comprising said FIFO portions contains a sequence of said states.

10. The controller of claim 9, said FIFO assembly comprises an output register and wherein a duration interval is derived from each said state, each said state persisting in said output register for said duration interval.

11. A method of controlling a system instantaneously specified by a plurality of parameters, said system including a clock device for synchronous operation, comprising the steps of:

initializing said plurality of parameters for defining each said state to default values thereof,

prescribing a progression of states at subsequent adjacent discrete times, comprising

assigning a duration to each state,

characterizing each state by the changes in value from the preceding state of one or more said parameters,

transfering only said changed values to a corresponding plurality of latched data registers, said latched registers corresponding to operand parameters, and also transferring content of said latched registers to a respective computational cell and computing the resultant of said operand parameters and retaining same in a latched resultant register,

communicating the parameters retained from each said latched register and each said resultant register and corresponding duration to an asynchronous-to-synchronous buffer,

presenting said parameters and resultants to an output in synchronous relation to said clocking device, and

maintaining said output for said corresponding duration.

12. The method of controlling the system of claim 11, wherein said operand parameters transferred to said latched registers comprise, at least, values proportional to RF phase, RF amplitude, and RF frequency.

13. The method of controlling the system of claim 11, wherein said operand parameters transferred to said latched registers comprise, at least, magnetic gradient vector magnitude and magnetic gradient vector orientation.

14. A controller for producing a sequence of states derived from an input bus, each said state comprising a plurality of independent variables realized as digital values, each said variable expressed in a corresponding digital precision and said state further characterized by duration, said controller comprising:

a plurality of latched registers for receiving and retaining corresponding datums from said input bus, said latched registers communicating with a plurality of FIFO portions said portions including a state duration, each portion in correspondence with one said latched register, each said latched register in corresponding relationship with one said FIFO portion, and state persistence logic whereby each said state is produced at an output of said FIFO for a specified duration.

an incremental state generator wherein at least one said latched resister comprises an argument portion of said datum, an increment portion of said datum and an adder for modifying said argument through addition of said increment portion and communicates the result thereof both to a corresponding said latched register and to re-place the value held in said argument portion of said latched register.

15. The controller of claim 14, wherein selected said FIFO portions communicate with a source of RF power and control one or all of the RF phase, RF amplitude and RF frequency.