Dynamic gate with conditional keeper for soft error rate reduction

• US 7,053,663 B2
• Filed: 03/26/2002
• Issued: 05/30/2006
• Est. Priority Date: 03/26/2002
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Krishnamurthy, Ram, Hazucha, Peter, Karnik, Tanay, Alvandpour, Atila
• Primary Examiner(s): LE, DON P
• Application Number:
  US10/107,779
• Publication Number:
  US 20030185087A1
• Time in Patent Office: 1,526 Days
• Field of Search: 326 73- 98, 326/112, 326/119, 326/121
• US Class Current: 326/121
• CPC Class Codes: G11C 5/005 Circuit means for protection against loss of information of semiconductor storage devices
• CPC Class Codes: H03K 19/0963 using transistors of complementary type H03K19/0966 takes precedence

Abstract

A dynamic logic gate with a conditional keeper, the conditional keeper comprising a pMOSFET pull-up that switches ON only after the dynamic logic gate completes an evaluation so as to avoid contention with the pull-down network. By sizing the conditional keeper to be stronger than the half-keeper, embodiments may realize a significant reduction in soft error rates that are latched.

Claims

1. A dynamic gate comprising:

a node;

a pull-down network to conditionally discharge the node LOW during an evaluation phase; and

a pull-up to charge the node HIGH by switching ON during the evaluation phase, wherein the pull-up switches ON only if the pull-down network does not conditionally discharge the node LOW during the evaluation phase.

2. The dynamic gate as set forth in claim 1, further comprising a half-keeper connected to the node, wherein the pull-up is substantially stronger than the half-keeper.

3. The dynamic gate as set forth in claim 2, wherein the pull-up is substantially stronger than the half-keeper.

4. The dynamic gate as set forth in claim 1, wherein the pull-up comprises a delay element, a static gate, and a pMOSFET.

5. A dynamic gate comprising:

an input port to receive a clock signal;

a ground rail;

a power rail;

a node;

a pull-down network to provide a conditional low impedance path between the node and the ground rail only if the clock signal is HIGH;

a delay element to provide a signal indicative of a delayed clock signal, the delayed clock signal lagging in phase with respect to the clock signal; and

a pull-up to provide a low impedance path between the node and the power rail only if the node and delayed clock signal are HIGH.

6. The dynamic gate as set forth in claim 5, further comprising:

a static logic gate having a first input port connected to the node and a second input port connected to the delay element to provide an output logic signal;

wherein the output logic signal is LOW only if the node and delayed clock signal are HIGH, and

wherein the pull-up further comprises a pMOSFET coupled to the static logic gate to have a gate voltage equal to the output logic signal.

7. The dynamic gate as set forth in claim 6 further comprising a half-keeper, wherein the pMOSFET is substantially stronger than the half-keeper.

8. The dynamic gate as set forth in claim 5 further comprising a half-keeper, wherein the pull-up is substantially stronger than the half-keeper.

9. A dynamic gate comprising:

an input port to receive a clock signal;

a node having a node signal;

a pull-down network connected to the node to conditionally discharge the node HIGH only if the clock signal is HIGH;

a pull-up pMOSFET having a drain connected to the node and having a gate; and

a static logic gate having a first input port to receive the clock signal, a second input port connected to the node, an output port connected to the gate of the pull-up pMOSFET;

the static logic gate to provide a logic signal indicative of a delayed version of the clock signal, and to provide at its output port a NAND function of the logic signal and the node signal.

10. The dynamic gate as set forth in claim 9, the static logic gate further comprising a delay element.

11. The dynamic gate as set forth in claim 10, further comprising a half-keeper substantially weaker than the pull-up pMOSFET.

12. A computer system comprising:

a bus;

a memory unit coupled to the bus; and

a microprocessor comprising;

a node;

a pull-down network to conditionally discharge the node LOW during an evaluation phase; and

a pull-up to charge the node HIGH by switching ON during the evaluation phase, wherein the pull-up switches ON only if the pull-down network does not conditionally discharge the node LOW during the evaluation phase.

13. The computer system as set forth in claim 12, the microprocessor further comprising a half-keeper connected to the node, wherein the pull-up is substantially stronger than the half-keeper.