Voltage controlled oscillator with automatic band selector

• US 7,053,683 B2
• Filed: 05/27/2004
• Issued: 05/30/2006
• Est. Priority Date: 05/27/2004
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Li, Dandan
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): COX, CASSANDRA F
• Application Number:
  US10/855,459
• Publication Number:
  US 20050264330A1
• Time in Patent Office: 733 Days
• Field of Search: None
• US Class Current: 327/156
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/103 the additional signal being a digital signal
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

A method and circuit for selecting the band of a multi-band voltage controlled oscillator in a phase locked loop is described. In one implementation, the circuit comprises a voltage controlled oscillator, a selection circuit for selecting a band for the voltage controlled oscillator from a plurality of predetermined bands, a decision circuit for determining if the selection circuit should select a new band from the plurality of predetermined bands, and a charging circuit for adjusting the input voltage into the voltage controlled oscillator.

Claims

1. A phase-locked loop circuit comprising:

a voltage controlled oscillator having a voltage input terminal for receiving an input voltage;

a selection circuit coupled to said voltage controlled oscillator, wherein said selection circuit selects a band for said voltage controlled oscillator from a plurality of predetermined bands;

a decision circuit coupled to said selection circuit, wherein said decision circuit determines if said selection circuit should select a new band from said plurality of predetermined bands; and

a charging circuit coupled to said decision circuit and said voltage input terminal of said voltage controlled oscillator, wherein said charging circuit adjusts a voltage at said voltage input terminal of said voltage controlled oscillator responsive to a signal received from said decision circuit;

wherein said charging circuit adjusts said voltage at said voltage input terminal to a voltage selected to minimize a settling delay of said circuit.

2. A circuit as set forth in claim 1, wherein said decision circuit comprises:

a high trigger input, a low trigger input, a high reset input, and a low reset input;

an UP output, a DOWN output, and a Trigger output;

a plurality of flip-flops, said flip-flops configured to provide a high voltage level on said DOWN output responsive to a high voltage level received on said high trigger input and a high voltage level on said UP input responsive to a high voltage level received on said low trigger input.

3. A circuit as set forth in claim 2, wherein said flip-flops are D type flip-flops.

4. A circuit as set forth in claim 1, wherein said charging circuit comprises:

at least one current source;

at least one switch coupled between said current source and said input voltage.

5. A phase locked loop frequency synthesizer comprising a circuit as set forth in claim 1.

6. A phase-locked loop circuit comprising:

a voltage controlled oscillator having a voltage input terminal for receiving an input voltage;

a selection circuit coupled to said voltage controlled oscillator, wherein said selection circuit selects a band for said voltage controlled oscillator from a plurality of predetermined bands;

a decision circuit coupled to said selection circuit, wherein said decision circuit determines if said selection circuit should select a new band from said plurality of predetermined bands; and

a charging circuit coupled to said decision circuit and said voltage input terminal of said voltage controlled oscillator, wherein said charging circuit adjusts a voltage at said voltage input terminal of said voltage controlled oscillator responsive to a signal received from said decision circuit;

wherein, when said decision circuit determines that said selection circuit should select a new band, it breaks the phase locked loop circuit.

7. A circuit as set forth in claim 6 wherein said decision circuit determines if said selection circuit should select a new band by comparing said input voltage to a first voltage, V_H, and second reference voltage, V_L, respectively, set to the high and low voltages for the presently selected band.

8. A circuit as set forth in claim 7 wherein the decision circuit controls the charging circuit to adjust said voltage at said voltage input terminal of said voltage controlled oscillator to a third reference voltage, V_H−

Δ

1, that is less than V_H and greater than V_L when said input voltage is greater than said first reference voltage and to a fourth reference voltage, V<sub>L+Δ

2</sub>, that is greater than V_L and less than V<sub>H−

Δ

1</sub> when said input voltage is less than V_L.

9. A circuit as set forth in claim 8 wherein V_H−

Δ

1 and V<sub>L+Δ

2</sub> are, respectively, the high and low optimal usable limits within the presently selected band.

10. A circuit as set forth in claim 9 wherein the decision circuit further disables the charging circuit and closes the phase locked loop after the charging circuit adjusts said voltage at said input voltage terminal.

11. A phase-locked loop circuit comprising:

a voltage controlled oscillator having a voltage input terminal for receiving an input voltage;

a selection circuit coupled to said voltage controlled oscillator, wherein said selection circuit selects a band for said voltage controlled oscillator from a plurality of predetermined bands;

a decision circuit coupled to said selection circuit, wherein said decision circuit determines if said selection circuit should select a new band from said plurality of predetermined bands; and

a charging circuit coupled to said decision circuit and said voltage input terminal of said voltage controlled oscillator, wherein said charging circuit adjusts a voltage at said voltage input terminal of said voltage controlled oscillator responsive to a signal received from said decision circuit;

wherein said selection circuit comprises;

a shift register having a plurality of outputs values, said shift register comprising;

at least one multiplexer having a multiplexer output; and

at least one flip-flop coupled to said multiplexer output;

wherein said shift register provides an output from said plurality of outputs values responsive to a signal from said decision circuit and wherein each output corresponds to a particular band in said plurality of predetermined bands for said voltage controlled oscillator.

12. A method for automatic band selection in a phase locked loop comprising a multi-band voltage controlled oscillator having a plurality of bands, said method comprising the steps of:

1) measuring an input voltage to the voltage controlled oscillator;

2) determining if said input voltage is outside of predetermined voltage levels;

3) selecting a different band from said plurality of bands; and

4) resetting said input voltage.

13. The method as set forth in claim 12 wherein step (4) comprises resetting said input voltage to a voltage chosen to minimize a settling delay of said circuit.

14. The method as set forth in claim 12 wherein step (3) comprises:

3.1) comparing said input voltage to four reference voltages;

V_H, V<sub>H−

Δ

1</sub>, V_L, and V<sub>L+Δ

2</sub>;

3.2) disabling said phase locked loop if said input voltage is higher than V_H or lower than V_L;

3.3) changing to a higher band when the input voltage is higher than V_H; and

3.4) changing to a lower band when the input voltage is lower than V_L.

15. The method as set forth in claim 14 wherein step (4) comprises:

4.1) charging the input voltage to V<sub>L+Δ

2</sub> when the input voltage is less than V<sub>L+Δ

2</sub>; and

4.2) discharging the input voltage to V<sub>H−

Δ

1</sub> when the input voltage is greater than V<sub>H−

Δ

1</sub>.

16. The method as set forth in claim 15 further comprising the step of:

(5) re-enabling said phase locked loop.

17. The method as set forth in claim 16 wherein V_H is the high voltage of the presently selected band, V_L is the low voltage for the presently selected band, V_H−

Δ

1 is the high optimal usable limit within the presently selected band and V<sub>L+Δ

2</sub> is the low optimal usable limit within the presently selected band.

18. The method as set forth in claim 12, wherein the step of determining if said input voltage is outside of predetermined voltage levels comprises:

comparing said input voltage with a plurality of reference voltages.

19. The method as set forth in claim 12, wherein the step of resetting said input voltage comprises:

charging said input voltage to a first predetermined level when said input voltage is less than said predetermined level; and

discharging said input voltage to a second predetermined level when said input voltage is greater than said second predetermined level.