Datapath architecture for high area efficiency

• US 7,054,178 B1
• Filed: 09/06/2002
• Issued: 05/30/2006
• Est. Priority Date: 09/06/2002
• Status: Active Grant

• Current Assignee: Etron Technology Inc
• Original Assignee: Etron Technology Inc
• Inventors: Shiah, Chun, Wang, Ming-Hung, Shen, Chun-Chi
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US10/236,384
• Time in Patent Office: 1,362 Days
• Field of Search: 365/51, 365/63, 365/205, 365/207, 365/208, 365/203, 365/230.03, 365/230.06
• US Class Current: 365/51
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out

Abstract

A particular DRAM data path architecture is disclosed. In accordance with this invention, the sharing of MDQ sense amplifiers simplifies the circuit design of the memory sub array. Fewer MDQ sense amplifiers and fewer unique MDQ lines leads to a reduced chip layout area. The high address bit of the word line row address (RA) is used to select a particular main data sense amp by means of a control switch. Not only are the sense amplifiers multiplexed for the new sub array, but the data I/O are multiplexed as well, leading to a significant reduction in the number of circuits required.

Claims

1. Dynamic Random Access, DRAM, data path circuitry comprising:

an array of memory cells,

a bit line attached to each of said memory cells,

a word line attached to each of said memory cells,

a bit line sense amplifier connected to each of said bit lines,

a bit switch which connects the output of bit line sense amplifiers to a local data line,

a local data line switch which connects multiple local data lines to a main data line,

a main data line sense amplifier connected to said main data lines, and

a main data line switch connected to each of said main data line sense amplifiers, wherein a memory data input bus and data output bus are multiplexed onto a single data bus in order to save semiconductor area, wherein a high address bit of a word line row address is used to select a particular main data sense amplifier by means of a control switch.

2. The DRAM data path circuitry of claim 1 wherein said array of memory cells store 1'"'"'s and 0'"'"'s and are configurable as one or multiple sub-arrays.

3. The DRAM data path circuitry of claim 1 wherein said bit lines are connected to each of said memory cells for purposes of delivering Write data or retrieving Read data from said memory cells.

4. The DRAM data path circuitry of claim 1 wherein said word lines are attached to each of said memory cells in order to address and accesss said memory cells in order to Read or Write said cells.

5. The DRAM data path circuitry of claim 1 wherein said bit line sense amplifier is used to sense whether said bit line has a voltage level which indicates a logical ‘

1’

level or a logical ‘

0’

level.

6. The DRAM data path circuitry of claim 1 wherein said a bit switch which connects the output of said bit line sense amplifier to a local data line.

7. The DRAM data path circuitry of claim 1 wherein said local data line provides routing with less wires than the full complement of bit lines in order to save semiconductor area.

8. The DRAM data path circuitry of claim 1 wherein said local data line switch which connects multiple local data lines to a main data line in order to save semiconductor area.

9. The DRAM data path circuitry of claim 1 wherein said main data line provides routing with less wires than the full complement of local data lines in order to save semiconductor area.

10. The DRAM data path circuitry of claim 1 wherein said main data line sense amplifier is connected to said main data lines.

11. The DRAM data path circuitry of claim 1 wherein said main data line switch is connected to each of said main data line sense amplifiers in order to multiplex two or more main data lines into individual main data line sense amplifiers in order to save semiconductor area.

12. The DRAM data path circuitry of claim 1 wherein a row address decoder is used to convert a memory address bus into said row address word line signals.

13. The DRAM data path circuitry of claim 1 wherein a column address decoder is used to convert a memory address bus into column address signals.

14. A method of designing a DRAM data path in order to reduce the circuit density comprising the steps of:

including an array of memory cells,

attaching bit lines to each of said memory cells,

attaching word lines to each of said memory cells,

connecting bit line sense amplifiers to each of said bit lines,

connecting bit switches from the output of bit line sense amplifiers to a local data line,

connecting local data line switches from multiple local data lines to a main data line,

connecting a main data line sense amplifier to said main data lines, and

connecting main data line switches to each of said main data line sense amplifiers, wherein a memory data input bus and data output bus are multiplexed onto a single data bus in order to save semiconductor area, wherein a high address bit of a word line row address is used to select a particular main data sense amplifier by means of a control switch.

15. The method of claim 14 wherein the designing of said array of memory cells involves the storing of 1'"'"'s and 0'"'"'s and the configuring as one or multiple sub-arrays.

16. The method of claim 14 wherein the designing of said bit lines involves the connecting to each of said memory cells for purposes of delivering Write data or retrieving Read data from said memory cells.

17. The method of claim 14 wherein the designing of said word lines involves attaching to each of said memory cells in order to address and accesss said memory cells in order to Read or Write said cells.

18. The method of claim 14 wherein the designing of said bit line sense amplifier involves sensing whether said bit line has a voltage level which indicates a logical ‘

1’

level or a logical ‘

0’

level.

19. The method of claim 14 wherein the designing of said bit switch involves connecting the output of said bit line sense amplifier to a local data line.

20. The method of claim 14 wherein the designing of said local data line involves routing with less wires than the full complement of bit lines in order to save semiconductor area.

21. The method of claim 14 wherein the designing of said local data line switch involves connecting multiple local data lines to a main data line in order to save semiconductor area.

22. The method of claim 14 wherein the designing of said main data line involves routing with less wires than the full complement of local data lines in order to save semiconductor area.

23. The method of claim 14 wherein the designing of said main data line sense amplifier involves connecting to said main data lines.

24. The method of claim 14 wherein the designing of said main data line switch involves connecting to each of said main data line sense amplifiers in order to multiplex two or more main data lines into individual main data line sense amplifiers in order to save semiconductor area.

25. The method of claim 14 wherein the designing of a row address decoder involves using it to convert a memory address bus into said row address word line signals.

26. The method of claim 14 wherein the designing of a column address decoder involves using it to convert a memory address bus into column address signals.