Double-high memory system compatible with termination schemes for single-high memory systems

• US 7,054,179 B2
• Filed: 10/30/2003
• Issued: 05/30/2006
• Est. Priority Date: 10/30/2003
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Martinez, Idis Ramona, Schumacher, Derek Steven, Cogdill, Mike
• Primary Examiner(s): Dinh, Son T.
• Application Number:
  US10/698,709
• Publication Number:
  US 20050094425A1
• Time in Patent Office: 943 Days
• Field of Search: 365/51, 365/61, 365/63
• US Class Current: 365/63
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: H05K 1/023 using auxiliary mounted passive components or auxiliary substances printed passive components H05K1/16
• CPC Class Codes: H05K 1/14 Structural association of two or more printed circuits providing electric connection to or between printed circuits H05K1/11, H01R12/00

Abstract

A double-high memory system compatible with termination schemes for single-high memory systems. The system includes an interface for input and output of data. A plurality of memory units is configured in two rows. A transmission line couples the plurality of memory units and the interface. The double-high memory system is provided in a non-stacked arrangement.

Claims

1. A double-high memory system compatible with termination schemes for single-high memory systems comprising:

an interface for input and output of data;

a plurality of memory units configured in two rows; and

a transmission line coupling said plurality of memory units to said interface, wherein a double-high memory module is provided in a non-stacked arrangement, and wherein said plurality of memory units is coupled together in a daisy chain configuration.

2. The double-high memory module of claim 1, wherein an impedance is situated between said connector and said two memory units.

3. The double-high memory module of claim 2, wherein said impedance is a resistor.

4. The double-high memory module of claim 2, wherein said impedance is a 22 ohm resistor.

5. The double-high memory system of claim 1, wherein said memory modules are dual inline memory modules.

6. The double-high memory module of claim 1, wherein said memory units are DDR SDRAM.

7. The double-high memory module of claim 1, wherein said third transmission line is one inch in length.

8. A system comprising:

a bus controller;

a plurality of memory module connectors coupled to said bus controller;

a single-high memory module coupled to a first of said connectors;

a double-high memory module coupled to a second of said connectors;

said double-high memory module comprising;

an interface for input and output of data;

a plurality of memory units configured in two rows; and

a transmission line coupling said plurality of memory units to said interface,

wherein a double-high memory module is provided in a non-stacked arrangement.

9. The double-high memory module of claim 8, further comprising a second transmission line connected to the first of two memory units that are coupled together via a third transmission line in a daisy chain configuration.

10. The double-high memory module of claim 8, further comprising two separate equal length transmission lines, wherein each of said equal length transmission lines connects to one of two memory units.

11. The double-high memory module of claim 8, wherein an impedance is situated between said connector and said two memory units.

12. The double-high memory module of claim 10, wherein said two separate transmission lines are symmetrically configured and signal transmission is balanced on each of said transmission lines.

13. The double-high memory module of claim 10, wherein each of two substantially equal length transmission lines connects to one of two memory units.

14. The double-high memory module of claim 11, wherein said impedance is a resistor.

15. The double-high memory module of claim 11, wherein said impedance is a 22 ohm resistor.

16. The double-high memory module of claim 8, wherein said memory module is a dual inline memory module.

17. The double-high memory module of claim 8, wherein said memory units are DDR SDRAM.

18. The double-high memory module of claim 9, wherein said transmission line is one inch in length.

19. A method for operating a double-high memory system compatible with termination schemes for single-high memory systems comprising:

receiving data into an intefface for input and output of data; and

storing and retrieving data from a plurality of memory units configured in two rows, wherein

a transmission line couples said plurality of memory units to said interface, wherein said double-high memory module is provided in a non-stacked arrangement, and wherein said plurality of memory units is coupled together in a daisy chain configuration.

20. The method claim 19, wherein an impedance is situated between said interface and said two memory units.

21. The method of claim 20, wherein said impedance is a resistor.

22. The method of claim 20, wherein said impedance is a 22 ohm resistor.

23. The method of claim 20, wherein said memory module is a dual inline memory module.

24. The method of claim 19, wherein said memory units are DDR SDRAM.

25. The method of claim 19, wherein said transmission line is one inch in length.