Non-volatile SRAM cell having split-gate transistors

• US 7,054,194 B2
• Filed: 06/27/2003
• Issued: 05/30/2006
• Est. Priority Date: 06/28/2002
• Status: Expired due to Fees

• Current Assignee: Brilliance Semiconductor Incorporated
• Original Assignee: Brilliance Semiconductor Incorporated
• Inventors: Yang, Hung-Ming, Liaw, Shion-Hau
• Primary Examiner(s): Yoha, Connie C.
• Application Number:
  US10/607,200
• Publication Number:
  US 20040001373A1
• Time in Patent Office: 1,068 Days
• Field of Search: 365/185.08, 365/185.01, 365/154, 365/185.22, 365/185.26, 365/185.29
• US Class Current: 365/185.08
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down

Abstract

This specification discloses a non-volatile static random access memory (SRAM) cell with the feature of keeping data even after the power is turned off. It includes a static random access unit and a non-volatile memory unit. Therefore, it has the random access property of the SRAM normally. After the power is turned off, it can store data in the non-volatile memory unit, so that the data can be automatically restored to the static random access unit from the non-volatile memory unit when the power is turned on.

Claims

1. A non-volatile static random access memory (SRAM) cell, comprising:

an SRAM unit, which receives a 1-bit datum, temporarily stores the 1-bit datum, and transmits the 1-bit datum for normal operations; and

a non-volatile memory unit, which connects to the SRAM unit for storing the 1-bit datum in the SRAM unit before power is turned off (storage operation), keeping the 1-bit datum (storage operation), recovering the 1-bit datum back to the SRAM unit once the power supply is resumed (recovery operation), and erasing the 1-bit after the recovery operation is completed (erase operation), the non-volatile memory unit further including two split-gate transistors, each of the split-gate transistors including a control gate, a source and a drain, the control gates of the split-gate transistors being connected, the sources of the split-gate transistors being connected and having a same voltage level, the drains of the split-gate transistors storing the 1-bit datum in the SRAM unit;

wherein a voltage on the control gates of the split-gate transistors is higher than that a voltage on the sources of the split-gate transistors during the storage operation.

2. The non-volatile SRAM cell of claim 1, wherein the SRAM unit further comprises a pair of inverters and two n-channel metal oxide semiconductor field effect transistors (nMOSFET'"'"'s), the gates of the nMOSFET'"'"'s connecting to a word line.

3. The non-volatile SRAM cell of claim 1, wherein the voltage on the control gates of the split-gate transistors is lower than 0V and the voltage on sources of the split-gate transistors is higher than 5V during the erase operation.

4. The non-volatile SRAM cell of claim 1, wherein the voltage on the control gates of the split-gate transistors is 0V and the voltage on the sources of the split-gate transistors is 0V during the normal operation.

5. The non-volatile SRAM cell of claim 1, wherein the voltage on the control gates of the split-gate transistors is equal to the voltage on the sources of the split-gate transistors during the recovery operation.

6. The non-volatile SRAM cell of claim 1, wherein a voltage on the word line of the SRAM unit is pulled down to a low level during the recovery operation, the erase operation, and the storage operation.

13. The non-volatile SRAM cell of claim 1, wherein the voltage on the control gates of the split-gate transistors is 0V and the voltage on the sources of the split-gate transistors is floating during the normal operation.

7. A non-volatile static random access memory (SRAM) cell, comprising:

an SRAM unit, which comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor, wherein the first transistor and the third transistor form a first inverter, the second transistor and the fourth transistor form a second inverter, the gates of the first transistor and the third transistor are connected to the drains of the fourth transistor and the sixth transistor, the gates of the second transistor and the fourth transistor are connected to the drains of the first transistor, the third transistor, and the fifth transistor, and the gates of the fifth transistor and the sixth transistor are connected with a word line; and

a non-volatile memory unit, which connects to the SRAM unit and comprises a seventh transistor and an eighth transistor, the seventh transistor and the eighth transistor being split-gate transistors, each of the split-gate transistors including a control gate, a source and a drain, the sources of the seventh and eight transistors being connected and having a same voltage level, the control gates of the seventh transistor and the eighth transistor being connected, the drain of the seventh transistor and the drains of the first transistor, the third transistor, and the fifth transistor are connected, and the eighth transistor is connected to the drains of the second transistor, the fourth transistor, and the sixth transistor;

wherein the SRAM unit receives a 1-bit datum, temporarily stores the 1-bit datum, and transmits the 1-bit datum for normal operations; and

the drains of the seventh and eighth transistors of the non-volatile memory unit stores the 1-bit datum in the SRAM unit before power is turned off (storage operation), keeps the 1-bit datum (storage operation), recovers the 1-bit datum back to the SRAM unit once the power supply is resumed (recovery operation), and erases the 1-bit after the recovery operation is completed (erase operation);

wherein a voltage on the control gates of the split-gate transistors is higher than that a voltage on the sources of the split-gate transistors during the storage operation.

8. The non-volatile SRAM cell of claim 7, wherein the first transistor, the second transistor, the fifth transistor, and the sixth transistor are nMOSFET'"'"'s, and the third transistor and the fourth transistor are pMOSFET'"'"'s.

9. The non-volatile SRAM cell of claim 7, wherein the voltage on the control gates of the split-gate transistors is lower than 0V and the voltage on sources of the split-gate transistors is higher than 5V during the erase operation.

10. The non-volatile SRAM cell of claim 7, wherein the voltage on the control gates of the split-gate transistors is 0V and the voltage on the sources of the split-gate transistors is 0V during the normal operation.

11. The non-volatile SRAM cell of claim 7, wherein the voltage on the control gates of the split-gate transistors is equal to the voltage on the sources of the split-gate transistors during the recovery operation.

12. The non-volatile SRAM cell of claim 7, wherein a voltage on the word line of the SRAM unit is pulled down to a low level during the recovery operation, the erase operation, and the storage operation.

14. The non-volatile SRAM cell of claim 7, wherein the voltage on the control gates of the split-gate transistors is 0V and the voltage on the sources of the split-gate transistors is floating during the normal operation.

15. A non-volatile static random access memory (SRAM) cell, comprising:

an SRAM unit, which receives a 1-bit datum, temporarily stores the 1-bit datum, and transmits the 1-bit datum for normal operations; and

a non-volatile memory unit, which connects to the SRAM unit for storing the 1-bit datum in the SRAM unit before power is turned off (storage operation), keeping the 1-bit datum (storage operation), recovering the 1-bit datum back to the SRAM unit once the power supply is resumed (recovery operation), and erasing the 1-bit after the recovery operation is completed (erase operation), the non-volatile memory unit further including two split-gate transistors, each of the split-gate transistors including a control gate, a source and a drain, the control gates of the split-gate transistors being connected, the sources of the split-gate transistors being connected and having a same voltage level, the drains of the split-gate transistors storing the 1-bit datum in the SRAM unit;

wherein a voltage on the control gates of the split-gate transistors is lower than 0V and a voltage on sources of the split-gate transistors is higher than 5V during the erase operation.