Multi level flash memory device and program method
First Claim
1. A method for programming a plurality of memory cells to a desired state, each cell having more than two possible states, comprising:
- applying at least one programming pulse to the cells;
verifying that each cell has reached the desired state;
selecting the cells that are programmed for a highest state; and
applying at least one additional programming pulse to the selected cells without further verifying their state.
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Abstract
We describe a multi level flash memory device and program method. The multi level flash memory device includes a plurality of memory cells, each storing an amount of charge indicative of more than two possible states and control circuitry coupled to the memory cells. The control circuitry to applying a programming voltage alternating with a verification voltage to the memory cells until all are at a desired state and applying at least one additional programming voltage to the cells in a highest state without applying a verification voltage. The method includes applying at least one programming pulse to the cells, verifying that each cell has reached the desired state, selecting the cells that are programmed for a highest state, and applying at least one additional programming pulse to the selected cells without further verifying their state.
101 Citations
24 Claims
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1. A method for programming a plurality of memory cells to a desired state, each cell having more than two possible states, comprising:
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applying at least one programming pulse to the cells; verifying that each cell has reached the desired state; selecting the cells that are programmed for a highest state; and applying at least one additional programming pulse to the selected cells without further verifying their state. - View Dependent Claims (2, 3, 4)
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5. A method of operating a memory device having a plurality of memory cells, each memory cell having more than two possible states, comprising:
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programming the cells to a desired state; applying a selected voltage to verify that the cells are in the desired state; programming the cells in a highest state to a higher level; and applying the selected voltage to read data from the cells. - View Dependent Claims (6, 7, 8)
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9. A method of enlarging the read margin between states in a plurality of memory cells, each memory cell having more than two possible states, comprising:
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applying programming pulses to the cells; verifying that each cell has reached a desired state; and applying at least one additional programming pulse to the cells in a highest state without any further verification of the state of those cells. - View Dependent Claims (10, 11, 12)
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13. A nonvolatile memory device comprising:
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a plurality of memory cells, each storing an amount of charge indicative of more than two possible states; and control circuitry coupled to the memory cells, the control circuitry to apply programming pulses alternating with a verification voltage to the memory cells until all are at a desired state and to apply at least one additional programming pulse to the cells in a highest state without applying a verification voltage. - View Dependent Claims (14, 15, 16)
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17. A nonvolatile memory device comprising:
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means for applying at least one programming pulse to the cells; means for verifying that each cell has reached the desired state; means for selecting the cells that are programmed for a highest state; and means for applying at least one additional programming pulse to the selected cells without further verifying their state. - View Dependent Claims (18, 19, 20)
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21. A nonvolatile memory device comprising:
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memory cell means, each cell storing an amount of charge indicative of more than two possible states; and control means coupled to the memory cell means, the control means to apply programming pulses alternating with a verification voltage to the memory cell means until all are at a desired state and to apply at least one additional programming pulse to the memory cell means in a highest state without applying a verification voltage. - View Dependent Claims (22, 23, 24)
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Specification