Transistor layout configuration for tight-pitched memory array lines

• US 7,054,219 B1
• Filed: 03/31/2005
• Issued: 05/30/2006
• Est. Priority Date: 03/31/2005
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Matrix Semiconductor, Inc. (Western Digital Corporation)
• Inventors: Scheuerlein, Roy E., Petti, Christopher J., Bandyopadhyay, Abhijit, Kumar, Tanmay
• Primary Examiner(s): Dinh, Son T.
• Application Number:
  US11/095,905
• Time in Patent Office: 425 Days
• Field of Search: 365/230.06, 365/51, 365/63
• US Class Current: 365/230.06
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures

Abstract

A multi-headed word line driver circuit incorporates bent-gate transistors to reduce the pitch otherwise achievable for interfacing to tightly-pitched array lines. In certain exemplary embodiments, a three-dimensional memory array includes multiple memory blocks and array lines traversing horizontally across at least one memory block. Vertical active area stripes are disposed beneath a first memory block, and a respective plurality of bent-gate electrodes intersects each respective active area stripe to define individual source/drain regions. Every other source/drain region is coupled to a bias node for the active area stripe, and remaining source/drain regions are respectively coupled to a respective array line associated with the first memory block, thereby forming a respective first driver transistor for the respective array line.

Claims

1. An integrated circuit comprising:

a memory array comprising a plurality of memory blocks, said memory array having a plurality of array lines traversing horizontally across at least one memory block;

a plurality M of vertical active area stripes disposed at least partially beneath a first memory block;

a respective plurality of gate electrodes intersecting each respective active area stripe to define individual source/drain regions, every other source/drain region being coupled to a respective bias node for the respective active area stripe, and remaining source/drain regions being respectively coupled to a respective array line associated with the first memory block, thereby forming a respective first driver transistor for the respective array line; and

a connection area along one side of the first memory block for making a vertical connection from a respective array line associated with the first memory block to a respective electrode on a lower interconnection level which is coupled to the corresponding first driver transistor for said array line.

2. The integrated circuit as recited in claim 1 wherein:

the plurality M of vertical active area stripes is disposed entirely beneath the first memory block and thus disposed to one side of the connection area.

3. The integrated circuit as recited in claim 2 wherein the plurality M of active area stripes is formed within one well structure.

4. The integrated circuit as recited in claim 1 wherein:

a plurality of driver input nodes, each coupled to a respective first driver transistor in each respective active area stripe, thereby resulting in a plurality M of first driver transistors responsive to a single associated driver input node.

5. The integrated circuit as recited in claim 1 wherein pairs of adjacent gate electrodes within each of the plurality of active area stripes are respectively coupled together to form a single logical transistor.

6. The integrated circuit as recited in claim 1 wherein at least every other gate electrode within each respective active area stripe is bent so that adjacent gate electrodes are closer together at one side of the active area stripe than said adjacent gate electrodes are at the other side of the active area stripe.

7. The integrated circuit as recited in claim 6 wherein every gate electrode within each respective active area stripe is bent so that adjacent gate electrodes are closer together at one side of the active area stripe than said gate electrodes are at the other side of the active area stripe.

8. The integrated circuit as recited in claim 1 wherein:

half of said plurality M of active area stripes are disposed beneath a second memory block adjacent to the first memory block; and

the connection area is disposed between the two halves of said plurality M of active area stripes.

9. The integrated circuit as recited in claim 1 further comprising:

a plurality of second driver transistors respectively coupled to the plurality of first driver transistors, thereby providing respective first and second driver transistors coupled to said respective array line associated with the first memory block.

10. The integrated circuit as recited in claim 9 wherein:

half of said plurality M of active area stripes are disposed beneath a second memory block adjacent to the first memory block;

the connection area is disposed between the two halves of said plurality M of active area stripes; and

half of said plurality of second driver transistors are disposed beneath the second memory block.

11. The integrated circuit as recited in claim 9 wherein the second plurality of driver transistors comprises:

a plurality of active area regions, each including a pair of gate electrodes intersecting said active area region to define two outer source/drain regions and an inner source/drain region, said respective outer source/drain regions coupled respectively to a respective one of the array lines for the first block, and said respective inner source/drain regions coupled to a bias node associated with the second driver transistors.

12. The integrated circuit as recited in claim 1 further comprising:

a second plurality M of vertical active area stripes disposed at least partially beneath a third memory block that is adjacent to neither the first or the second memory blocks;

for each of the second plurality M of vertical active area stripes, a respective plurality of gate electrodes intersecting each respective active area stripe to define individual source/drain regions, every other source/drain region being coupled to a respective bias node for the respective active area stripe, and remaining source/drain regions being respectively coupled to a respective array line associated with the third memory block, thereby forming a respective first driver transistor for the respective array line; and

a connection area along one side of the third memory block for making a vertical connection from a respective array line associated with the third memory block to a respective electrode on a lower interconnection level which is coupled to the corresponding first driver transistor for said array line.

13. The integrated circuit as recited in claim 12 wherein each the plurality of driver input nodes is coupled to a respective first driver transistor in each respective one of the second plurality M of active area stripes, thereby resulting in a plurality M of first driver transistors associated with the first memory block and a plurality M of first driver transistors associated with the third memory block responsive to a single associated driver input node.

14. The integrated circuit as recited in claim 13 wherein:

said plurality of array lines traversing horizontally across at least one memory block comprise word lines; and

each memory block includes interleaved word lines, approximately half of which are coupled to associated driver transistors by way of a connection area on one side of the block, and the remaining ones are coupled to associated driver transistors by way of a connection area on the other side of the block.

15. The integrated circuit as recited in claim 14 wherein, in a given memory block, the word lines coupled to associated driver transistors by way of a connection area on one side of the given memory block are shared with word lines in an adjacent memory block thereto.

16. The integrated circuit as recited in claim 15 wherein:

the memory array comprises a three-dimensional memory array; and

each word line in a given memory block comprises a word line segment on each of at least two memory planes within the given memory block.

17. A computer-readable medium encoding an integrated circuit, said encoded integrated circuit as recited in claim 1.

18. An integrated circuit comprising:

a three-dimensional memory array having more than one memory plane, each plane comprising a plurality of array lines of a first type;

a plurality of array line driver circuits, a respective one for each respective array line;

wherein each array line driver circuit comprises at least one bent-gate transistor.

19. The integrated circuit as recited in claim 18 wherein said at least one bent-gate transistor comprising each array line driver circuit is disposed beneath the memory array.

20. The integrated circuit as recited in claim 18 wherein said bent-gate transistors are higher voltage devices relative to other transistors disposed within the integrated circuit.

21. The integrated circuit as recited in claim 20 wherein said bent-gate transistors are at least twice the nominal electrical length of other transistors disposed within the integrated circuit.

22. The integrated circuit as recited in claim 20 wherein each array line comprises an array line segment on each of more than one memory layer.

23. An integrated circuit comprising:

a memory array disposed above a dielectric layer, said memory array having a plurality of array lines traversing horizontally across at least a portion of the memory array; and

a plurality of array line driver circuits, a respective one for each respective array line, said plurality of array line driver circuits comprising a plurality of first driver transistors of a first conductivity type arranged generally in at least one column, at least some of which first driver transistors comprise bent-gate transistors disposed beneath the memory array.

24. The integrated circuit as recited in claim 23 wherein:

the memory array comprises a plurality of memory blocks, each array line traversing horizontally across at least one memory block.

25. The integrated circuit as recited in claim 24 wherein:

array line driver circuits associated with a respective memory block comprise active area regions arranged in at least one column of such regions beneath the respective memory block.

26. The integrated circuit as recited in claim 25 wherein:

each active area region within a column of such active area regions comprises a pair of first driver transistors; and

a respective first driver transistor within each column of such active area regions is coupled to a single respective driver input node.

27. The integrated circuit as recited in claim 25 wherein:

each array line driver circuit comprises a second driver transistor of a second conductivity type opposite the first conductivity type.

28. The integrated circuit as recited in claim 27 further comprising:

a connection area along each side of each memory block for making a respective vertical connection from respective array lines associated therewith to the corresponding array line driver circuit for said respective array line.