Non-synchronous semiconductor memory device having page mode read/write

• US 7,054,224 B2
• Filed: 05/23/2002
• Issued: 05/30/2006
• Est. Priority Date: 05/24/2001
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Takahashi, Hiroyuki, Nakagawa, Atsushi, Inaba, Hideo
• Primary Examiner(s): NGUYEN, VAN THU T
• Application Number:
  US10/478,369
• Publication Number:
  US 20040170081A1
• Time in Patent Office: 1,468 Days
• Field of Search: 365/189.02 X, 365/189.05, 365/233.5 O, 365/238.5 X
• US Class Current: 365/233.5
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits

Abstract

The present invention provides a non-synchronous semiconductor memory device configured as a pseudo-SRAM and capable of relaxing the limitation to address skew and improving the read rate. A data latch circuit 110 holds data having been read out of memory cells in a memory cell array 106 designated by a tow address included in an address ADD in a read mode. Upon transitions of column addresses A0, A1 included in the address, a multiplexer 111 sequentially and non-synchronously feeds out the data held in the data latch circuit 110 based on the column addresses A0, A1.

Claims

1. A semiconductor memory device configured to read out data from a memory cell connected to a bit line by triggering a transition of an address externally supplied, said semiconductor memory device including:

a hold circuit for reading out and holding, in a read mode, a plurality of data from memory cells designated by a row address and a part of a column address included in said address;

an input output control circuit for sequentially and non-synchronously feeding out said plurality of data held based on remaining addresses other than both said row address and said part of said column address; and

a control circuit that controls a second read operation based on a determination of whether said row address and said part of said column address correspond to an indefinite address that was provided during a first read operation.

4. The semiconductor memory device as claimed in claim 1, wherein said input output control circuit includes:

a multiplexer for selecting one of said plurality of data held by said hold circuit; and

a switch control circuit for non-synchronously switching a selection state of said multiplexer based on said remaining addresses.

5. The semiconductor memory device as claimed in claim 1, wherein said hold circuit takes in time-division said plurality of data having read out from said memory cells, based on said remaining addresses.

6. The semiconductor memory device as claimed in claim 1, wherein if only said remaining addresses are transitioned in a write mode, than a plurality of data are externally taken in a plurality of cycles defined by said remaining addresses and then held in said hold circuit, and said plurality of data as held are respectively written in said memory cells in a last cycle of said plurality of cycles.

7. The semiconductor memory device as claimed in claim 1, wherein if only said remaining addresses are transitioned in a write mode, then a plurality of data are externally taken in a plurality of cycles defined by said remaining addresses, and said plurality of data as held are respectively written in said memory cells in late-write.

2. A semiconductor memory device configured to read out data from a memory cell connected to a bit line by triggering a transition of an address externally supplied, said semiconductor memory device including:

a hold circuit for reading out and holding, in a read mode, a plurality of data, from memory cells designated by a row address and a part of a column address included in said address;

an input output control circuit for sequentially and non-synchronously feeding out said plurality of data held based on remaining addresses other than both said row address and said part of said column address; and

a control circuit for starting a read operation based on said row address and said part of said column address after a predetermined time has past from an external supply of said row address and said part of said column address, wherein said control circuit starts a read operation based on a row address and a part of a column address newly taken at a timing prior to said predetermined time if said row address and said part of said column address were transitioned during said read operation.

3. The semiconductor memory device as claimed in claim 2, wherein said control circuit compares said row address newly taken and said part of said column address newly taken to said row address previously taken and said part of said column address previously taken, and renders null said newly taken row address and said part of said newly taken column address if those addresses are identical with each other.