Modulator of phase shift keying (PSK) type

• US 7,054,382 B2
• Filed: 03/14/2002
• Issued: 05/30/2006
• Est. Priority Date: 12/13/2001
• Status: Active Grant

• Current Assignee: SK Keyfoundry Incorporated
• Original Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Inventors: Lee, Dae-Hun
• Primary Examiner(s): Bocure, Tesfaldet
• Assistant Examiner(s): Hoque, Nasrin
• Application Number:
  US10/096,871
• Publication Number:
  US 20030112894A1
• Time in Patent Office: 1,538 Days
• Field of Search: 375/130, 375/308, 375/279, 375/280, 375/282, 375/329, 375/333, 332/103, 455/102, 455/110, 455/112, 455/113
• US Class Current: 375/295
• CPC Class Codes: H04L 2027/0016 Stabilisation of local oscillators
• CPC Class Codes: H04L 2027/0018 Arrangements at the transmitter end
• CPC Class Codes: H04L 27/2089 with unbalanced quadrature channels

Abstract

A modulator phase shift keying modulator for performing data modulation by using the phase difference of each I/Q channel, comprising a data shifter for controlling delay of I/Q channel digital data at input terminals of the I/Q channels.

Claims

1. A phase shift keying type modulator for performing data modulation, comprising:

first and second digital-to-analog converting means for converting outputs of first and second data shifting means into analog signals respectively;

first and second filtering means for filtering outputs of the first and second digital-to-analog converting means respectively;

a mixing means for carrying outputs of the first and second filtering means with first and second carrier signals having a predetermined phase difference and generating one signal; and

a delay control means for detecting phase mismatch between outputs of the first and second filtering means and phase mismatch between the first and second carrier signals and controlling delay of the first and second data shifting means to compensate the phase mismatch.

2. The modulator as recited in claim 1, wherein each of said first and second data shifting means includes:

a plurality of shift registers, which are connected in series, operated in response to a clock signal; and

a plurality of switches, which are connected to each input terminal of the plurality of shift registers, for selectively outputting outputs of the shift registers.

3. The modulator as recited in claim 2, wherein the first data shifting means and the first digital-to-analog converting means are controlled by a first clock.

4. The modulator as recited in claim 3, wherein the second data shifting means and the second digital-to-analog converting means are controlled by a second clock.

5. The modulator as recited in claim 1, wherein the mixer includes:

an oscillator for generating the second carrier signal;

a phase shifter for generating the first carrier signal by shifting the second carrier signal by a predetermined phase difference;

a first multiplier for multiplying the output of the first filtering means by the second carrier signal;

a second multiplier for multiplying the output of the second filtering means by the first carrier signal; and

an adder for summing outputs of the first and second multipliers.

6. The modulator as recited in claim 5, wherein the phase shifter is a π

/2 phase shifter.

7. The modulator as recited in claim 1, wherein the first and second filtering means are a low pass filter.