Method and apparatus for multipath signal compensation in spread-spectrum communications systems

• US 7,054,396 B2
• Filed: 08/20/2002
• Issued: 05/30/2006
• Est. Priority Date: 08/20/2002
• Status: Active Grant

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: RF Micro Devices Incorporated (Qorvo, Inc.)
• Inventors: Shan, Peijun
• Primary Examiner(s): TRAN, KHANH C
• Application Number:
  US10/224,001
• Publication Number:
  US 20040037380A1
• Time in Patent Office: 1,379 Days
• Field of Search: 375147-148, 375/230, 375/232, 375/233, 375/285, 375346-349, 455/63.1, 455/65, 455/67.13, 455/132, 455133-137
• US Class Current: 375/346
• CPC Class Codes: H04B 1/7103 the interference being multiple access interference
• CPC Class Codes: H04B 1/7107 Subtractive interference cancellation
• CPC Class Codes: H04B 1/7115 Constructive combining of multi-path signals, i.e. RAKE receivers
• CPC Class Codes: H04B 1/7117 Selection, re-selection, allocation or re-allocation of paths to fingers, e.g. timing offset control of allocated fingers
• CPC Class Codes: H04B 2001/70706 using a code tracking loop, e.g. a delay locked loop
• CPC Class Codes: H04L 2025/03375 Passband transmission
• CPC Class Codes: H04L 25/03006 Arrangements for removing intersymbol interference

Abstract

The equalizer of the present invention operates on input multipath signal samples, preferably at chip or sub-chip resolution, to remove or substantially cancel the effects of one or more secondary signals from the main path signal. Using predetermined path information for one or more of the secondary path signals, including magnitude, phase, and time offset relative to the main path signal, the equalizer compensates input multipath signal samples by subtracting estimated secondary signal values from the input samples. For each input sample, the equalizer forms a sliced sample, where the sliced sample represents a nominal phase value defined by the modulation scheme used in the original chip or symbol transmission that is closest in value to the actual phase of the input sample. These sliced samples are held in a running buffer and used, in combination with the predetermined path information and scaling logic, to form the estimated secondary signal values for compensating the input samples.

Claims

1. An apparatus comprising:

a) a compensation circuit adapted to receive input samples from a received multipath signal and compensate the input samples using secondary signal estimates to form compensated samples;

b) a hard-decision circuit adapted to receive the compensated samples and determine a nominal phase value for each input sample, wherein said hard-decision circuit outputs a selected one from a defined set of nominal phase values as the nominal phase value;

c) a buffer circuit adapted to receive the nominal phase value from said hard-decision circuit and maintain a running sequence of past nominal phase values in successive buffer positions corresponding to successively greater sample time offsets with respect to the current input sample;

d) a buffer interface circuit adapted to receive path delay information corresponding to a secondary path signal and provide a selected past nominal phase value, one or more early nominal phase values, and one or more later nominal phase values by retrieving the past nominal phase value currently held in one of said buffer positions corresponding to a sample time offset equal to the received path delay information and further retrieving the one or more early nominal phase values from one or more of said buffer positions which precede said buffer position corresponding to the sample time offset and the one or more later nominal phase values from one or more of said buffer positions which follow said buffer position corresponding to the sample time offset; and

e) an estimation circuit comprising

i) memory and calculation logic adapted to receive the selected past nominal phase value selected from said buffer interface circuit, receive and store magnitude and phase information corresponding to the secondary path signal in the received multipath signal, and produce an unscaled secondary signal estimate for a current input sample based on the magnitude and phase information and the past nominal phase value derived from prior input samples;

ii) scaling logic adapted to produce a scaling factor based on the one or more early nominal phase values and the one or more later nominal phase values preceding and following said selected past nominal phase value; and

iii) multiplication logic adapted to combine the unscaled secondary signal estimate and the scaling factor to produce a current secondary signal estimate;

wherein said apparatus is operative to remove secondary path signal interference from the input samples for output as compensated samples to an associated communications system based directly or indirectly upon successive current secondary signal estimates.

2. The apparatus of claim 1 wherein the scaling logic is adapted to produce a scaling factor equal to 0 when the early and later nominal phase values are at opposite constellation points, wherein the opposite constellation points are defined by a modulation scheme associated with the received multipath signal.

3. The apparatus of claim 2 wherein the scaling logic is adapted to produce a scaling factor equal to ½

when both I and Q components of the received multipath signal transition either to or from zero, wherein the transition either to or from zero occurs when the early and later nominal phase values are at neighboring constellation points and said neighboring constellation points are defined by the modulation scheme associated with the received multipath signal.

4. The apparatus of claim 3 wherein the scaling logic is adapted to produce a scaling factor equal to 1 when the early and later nominal phase values are at a same constellation point, wherein the same constellation point is defined by the modulation scheme associated with the received multipath signal.

5. The apparatus of claim 1 wherein said multiplication logic is further adapted to provide said compensation circuit with the current secondary signal estimate, wherein said compensation circuit compensates the current input sample using the current secondary signal estimate.

6. The apparatus of claim 1 further comprising at least one additional estimation circuit adapted to receive additional magnitude and phase information corresponding to additional secondary signals in the received multipath signal, wherein said buffer interface is further adapted to receive additional path delay information corresponding to the additional secondary signals, and further wherein said at least one additional estimation circuit is adapted to output additional current secondary signal estimates based on the additional magnitude and phase information and additional scaling factors in combination with additional selected past nominal phase values and additional selected early and later past nominal phase values selected by said buffer interface circuit from said buffer circuit based on the additional path delay information.

7. The apparatus of claim 6 further comprising summing logic adapted to combine the current secondary signal estimate and the additional current secondary signal estimates and provide said compensation circuit with the secondary signal estimates.

8. The apparatus of claim 1 wherein the secondary path signal is of a first type of secondary path signal having a path delay that is longer than a path delay of a main path signal within the received multipath signal.

9. The apparatus of claim 1 further comprising:

a delay circuit adapted to receive compensated samples from said compensation circuit and to output delayed compensated samples; and

a second compensation circuit adapted to receive delayed compensated samples and second secondary signal estimates from said estimation circuit and to output finally compensated samples based on the delayed compensated samples and the second secondary signal estimates, wherein the second secondary signal estimates correspond to one or more of a second type of secondary signals within the received multipath signal having a path delay less than the path delay of the main path signal.

10. The apparatus of claim 9 further comprising one or more second estimation circuits being adapted to receive magnitude and phase information for one or more of the second type of secondary signal and said buffer interface circuit is further adapted to receive path delay information for the one or more of the second type of secondary signal, and said one or more second estimation circuits are further adapted to output the second secondary signal estimates based on receiving additional selected past nominal phase values from said buffer circuit via said buffer interface circuit based on the path delay information for the one or more of the second type of secondary path signal and producing additional scaling factors derived from additional early and later values selected from said buffer circuit via said buffer interface circuit.

11. The apparatus of claim 10 further comprising a second summing logic adapted to combine the one or more second secondary signal estimates and provide said second compensation circuit with the second secondary signal estimates.

12. The apparatus of claim 1 wherein said buffer circuit is further adapted to receive a buffer clock signal, and is operative to maintain the running sequence of past nominal phase values based on updating the running sequence of past nominal phase values with a current nominal phase value determined for a current input sample in response to a defined transition of the buffer clock signal.

13. The apparatus of claim 12 wherein a number D of said successive buffer positions within said buffer circuit defines a maximum sample time offset between an oldest past nominal phase value in a last buffer position and a current input sample, and further wherein a buffer clock signal frequency determines a time resolution between consecutive said buffer positions and a maximum time delay between said last buffer position and the current input sample.

14. The apparatus of claim 13 wherein said apparatus is configured such that the number D of said successive buffer positions within said buffer circuit represents a time delay between said last buffer position and the current input sample that is greater than one symbol time, wherein a symbol time is defined by a modulation scheme associated with the received multipath signal.

15. The apparatus of claim 13 wherein said apparatus is configured to operate on input samples having a time resolution no greater than one chip time, wherein a chip time is defined by a spread spectrum scheme associated with the received multipath signal.

16. The apparatus of claim 13 wherein the buffer clock signal frequency is proportional to an input sample rate associated with input samples from the received multipath signal.

17. The apparatus of claim 1 wherein said compensation circuit comprises a summing circuit adapted to receive input samples and secondary signal estimates, said summing circuit adapted to output each compensated sample as a difference between a given input sample and a corresponding secondary signal estimate.

18. The apparatus of claim 17 further comprising a decimation circuit positioned in advance of said summing circuit in an input sample signal path within said compensation circuit, wherein said decimation circuit is adapted to decimate the input samples to reduce an input sample rate associated with the input samples to a decimated sample rate, and further wherein said summing circuit receives decimated input samples from said decimation circuit instead of input samples directly from the received multipath signal.

19. The apparatus of claim 18 wherein said decimation circuit is further adapted to receive configuration information from the associated communications system, and wherein said configuration information determines the decimated sample rate.

20. The apparatus of claim 18 wherein said compensation circuit is further adapted to modify a buffer clock signal provided to said buffer circuit based on the decimated sample rate, and wherein said buffer circuit is further adapted to update the running sequence of past nominal phase values with a current nominal phase value determined for a current decimated input sample in response to a defined transition of the buffer clock signal.

21. The apparatus of claim 1 wherein said memory and calculation logic is further adapted to receive and store a complex coefficient representing a magnitude and phase of the secondary path signal relative to a main path signal within the received multipath signal as part of the received magnitude and phase information, and wherein the unscaled secondary signal estimate is produced by rotating the phase of the complex coefficient using the selected one of the past nominal phase values retrieved from said buffer circuit via said buffer interface circuit.

22. The apparatus of claim 21 wherein said estimation circuit outputs successive secondary signal estimates corresponding to successive input samples based on producing successive unscaled secondary signal estimates by rotating the phase of the complex coefficient with successive past nominal phase values retrieved from the selected one of said buffer positions corresponding to the sample time offset and multiplying the successive unscaled secondary signal estimates by successive scaling factors produced by said scaling logic.

23. An apparatus comprising:

a) a first compensation circuit adapted to receive input samples from a received multipath signal and compensate input samples using first secondary signal estimates to form first compensated samples;

b) a delay circuit adapted to receive the first compensated samples and output delayed first compensated samples;

c) a second compensation circuit adapted to receive the delayed first compensated samples and compensate the delayed first compensated samples using second secondary signal estimates to form second compensated samples;

d) a hard-decision circuit adapted to receive the compensated input samples and determine a nominal phase value for each first compensated sample, wherein said hard-decision circuit outputs a selected one from a defined set of nominal phase values as the nominal phase value;

e) a buffer circuit adapted to receive the nominal phase value from said hard-decision circuit and maintain a running sequence of past nominal phase values in successive buffer positions corresponding to successively greater sample time offsets with respect to the current input sample based on receiving the nominal phase values output from said hard-decision circuit; and

f) a buffer interface circuit adapted to receive path delay information corresponding to one or more of first and second types of secondary path signals, and further adapted to provide selected past nominal phase values and associated early and later nominal phase values by retrieving the past nominal phase values currently held in said buffer circuit from said buffer positions corresponding to sample time offsets equal to the received path delay information and further retrieving the early nominal phase values currently held in said buffer circuit from said buffer positions which precede said buffer positions corresponding to the sample time offsets and the later nominal phase values currently held in said buffer circuit from said buffer positions which follow said buffer positions corresponding to the sample time offsets;

g) one or more first estimation circuits each adapted to provide a current first secondary signal estimate for the first type of secondary path signal, each of said first estimation circuits comprising;

i) first memory and calculation logic adapted to receive the selected past nominal phase values, receive and store magnitude and phase information corresponding to a secondary path signal of the first type in the received multipath signal, and produce an unscaled first secondary signal estimate for an input sample based on the magnitude and phase information and a one of the selected past nominal phase values derived from prior input samples;

ii) first scaling logic adapted to produce a scaling factor based on one or more early and later nominal phase values preceding and following the one of the selected past nominal phase values; and

iii) first multiplication logic adapted to combine said unscaled first secondary signal estimate with said scaling factor to produce the current first secondary signal estimate; and

h) one or more second estimation circuits each adapted to provide a current second secondary signal estimate for the second type of secondary path signal, each of said second estimation circuits comprising

i) second memory and calculation logic adapted to receive the selected past nominal phase values, receive and store magnitude and phase information corresponding to a secondary path signal of the second type in the received multipath signal, and produce an unscaled second secondary signal estimate for an input sample based on the magnitude and phase information and a second one of the selected past nominal phase values derived from prior input samples;

ii) second scaling logic adapted to produce a scaling factor based on one or more early and later nominal phase values preceding and following the second one of the selected past nominal phase values; and

iii) second multiplication logic adapted to combine said unscaled second secondary signal estimate with said scaling factor to produce the current second secondary signal estimate;

wherein said apparatus is operative to remove secondary path signal interference for one or more of the first and second types of secondary path signals based either directly or indirectly upon one or more of the current first and current second secondary signal estimates, further wherein the first type of secondary signal has a path delay greater than a path delay of a main path signal in the received multipath signal and the second type of secondary path signal has a path delay less than the path delay of the main path signal.

24. The apparatus of claim 23 wherein the first and second scaling logics are adapted to produce a scaling factor equal to 0 when the early and later nominal phase values are at opposite constellation points, wherein the opposite constellation points are defined by a modulation scheme associated with the received multipath signal.

25. The apparatus of claim 24 wherein the first and second scaling logics are adapted to produce a scaling factor equal to ½

when both I and Q components of the received multipath signal transition either to or from zero, wherein the transition either to or from zero occurs when the early and later nominal phase values are at neighboring constellation points and said neighboring constellation points are defined by the modulation scheme associated with the received multipath signal.

26. The apparatus of claim 25 wherein the first and second scaling logics are adapted to produce a scaling factor equal to 1 when the early and later nominal phase values are at a same constellation point, wherein the same constellation point is defined by the modulation scheme associated with the received multipath signal.

27. The apparatus of claim 23 wherein said first multiplication logic in the one or more first estimation circuits is further adapted to provide said first compensation circuit with the first secondary signal estimates, wherein the first secondary signal estimates are successive current secondary signal estimates.

28. The apparatus of claim 23 wherein said second multiplication logic in the one or more second estimation circuits is further adapted to provide said second compensation circuit with the second secondary signal estimates, wherein the second secondary signal estimates are successive secondary signal estimates.

29. The apparatus of claim 23 further comprising first summing logic adapted to combine one or more current first secondary signal estimates and provide said first compensation circuit with the first secondary signal estimates.

30. The apparatus of claim 29 further comprising second summing logic adapted to combine one or more current second secondary signal estimates and provide said second compensation circuit with the second secondary signal estimates.

31. The apparatus of claim 23 wherein said second compensation circuit comprises a summing circuit adapted to receive delayed first compensated samples and second secondary signal estimates, said summing circuit adapted to output each second compensated sample as a difference between a given delayed first compensated sample and a corresponding second secondary signal estimate.

32. The apparatus of claim 23 wherein said first compensation circuit comprises a decimation circuit adapted to decimate the input samples from an input sample rate to a reduced decimated sample rate, and further comprises a summing circuit adapted to output first compensated samples as a difference between decimated input samples and first secondary signal estimates.

33. An apparatus comprising:

a) a delay circuit adapted to receive input samples from a received multipath signal and output delayed samples;

b) a compensation circuit adapted to receive the delayed samples and compensate the delayed samples using secondary signal estimates to form compensated samples;

c) a hard-decision circuit adapted to receive the input samples and output a nominal phase value for each input sample;

d) a buffer circuit adapted to receive the nominal phase value from said hard-decision circuit and maintain a running sequence of past nominal phase values in successive buffer positions corresponding to successively greater sample time offsets with respect to the current input sample based on receiving past nominal phase values output from the hard-decision circuit; and

e) a buffer interface circuit adapted to receive path delay information corresponding to the secondary path signal and provide a selected past nominal phase value, one or more early nominal phase values, and one or more later nominal phase values by retrieving the past nominal phase value currently held in one of said buffer positions corresponding to a sample time offset equal to the received path delay information and further retrieving the one or more early nominal phase values from one or more of said buffer positions which precede said buffer position corresponding to the sample time offset and the one or more later nominal phase values from one or more of said buffer positions which follow said buffer position corresponding to the sample time offset; and

g) an estimation circuit comprising

i) memory and calculation logic adapted to receive the selected past nominal phase value selected from said buffer interface circuit, receive and store magnitude and phase information corresponding to a secondary path signal in the received multipath signal, and produce an unscaled secondary signal estimate for a current input sample based on the magnitude and phase information and the past nominal phase value derived from prior input samples;

ii) scaling logic adapted to produce a scaling factor based on the one or more early nominal phase values and the one or more later nominal phase values preceding and following said selected past nominal phase value; and

iii) multiplication logic adapted to combine the unscaled secondary signal estimate and the scaling factor to produce a current secondary signal estimate;

wherein said apparatus is operative to remove secondary path signal interference from the received multipath signal due to the secondary path signal based directly or indirectly upon successive current secondary signal estimates.

34. The apparatus of claim 33 wherein the scaling logic is adapted to produce a scaling factor equal to 0 when the early and later nominal phase values are at opposite constellation points, wherein the opposite constellation points are defined by a modulation scheme associated with the received multipath signal.

35. The apparatus of claim 34 wherein the scaling logic is adapted to produce a scaling factor equal to ½

when both I and Q components of the received multipath signal transition either to or from zero, wherein the transition either to or from zero occurs when the early and later nominal phase values are at neighboring constellation points and said neighboring constellation points are defined by the modulation scheme associated with the received multipath signal.

36. The apparatus of claim 35 wherein the scaling logic is adapted to produce a scaling factor equal to 1 when the early and later nominal phase values are at a same constellation point, wherein the same constellation point is defined by the modulation scheme associated with the received multipath signal.

37. The apparatus of claim 33 further comprising at least one additional estimation circuit adapted to receive additional magnitude and phase information corresponding to additional secondary signals in the received multipath signal, wherein said buffer interface is further adapted to receive additional path delay information corresponding to the additional secondary signals, and further wherein said at least one additional estimation circuit is adapted to output additional current secondary signal estimates based on the additional magnitude and phase information and additional scaling factors in combination with additional selected past nominal phase values and additional selected early and later past nominal phase values selected by said buffer interface circuit from said buffer circuit based on the additional path delay information.

38. The apparatus of claim 37 further comprising summing logic adapted to combine the current secondary signal estimate and the additional current secondary signal estimates and provide said compensation circuit with the secondary signal estimates.

39. The apparatus of claim 33 wherein the secondary path signal is of a second type of secondary path signal having a path delay that is less than a path delay of a main path signal within the received multipath signal.