Method and system for bit-based data access

• US 7,054,964 B2
• Filed: 11/05/2004
• Issued: 05/30/2006
• Est. Priority Date: 07/30/2001
• Status: Expired due to Fees

• Current Assignee: Pixelworks Incorporated
• Original Assignee: VIXS Systems Incorporated (Pixelworks Incorporated)
• Inventors: Chan, Jason, Laksono, Indra
• Primary Examiner(s): SHIN, CHRISTOPHER B
• Application Number:
  US10/982,740
• Publication Number:
  US 20050066083A1
• Time in Patent Office: 571 Days
• Field of Search: 710 62- 71, 375/240, 725/135, 712220-248, 712/300, 345530-574, 365/230.05
• US Class Current: 710/65
• CPC Class Codes: H04N 19/40 using video transcoding, i.e. partial or full decoding of a coded input stream followed by re-encoding of the decoded output stream
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/56 Motion estimation with initialisation of the vector search, e.g. estimating a good candidate to initiate a search
• CPC Class Codes: H04N 19/59 involving spatial sub-sampling or interpolation, e.g. alteration of picture size or resolution
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 21/2365 Multiplexing of several video streams
• CPC Class Codes: H04N 21/4347 Demultiplexing of several video streams
• CPC Class Codes: H04N 9/8042 involving data reduction

Abstract

A system and a method for transcoding multiple media channels are provided. The system includes a first processor to parse a media data stream having one or more media data channels and a vector processor to decompress, scale, and then compress the parsed media channel. A parsed media data channel, in one embodiment, is accessed using a bit manipulator and packetized into decoder instruction packets and transmitted to the vector processor using a sequencer. The vector processor decompresses the decoder instruction pacets, scales a macroblock generated from the packets, and then compresses the scaled macroblock. As a result, the scaled and compressed output has less data associated with the media channel, allowing for faster and/or more efficient storage or transmission. A reduced sized scale buffer is associated with another disclosed embodiment.

Claims

1. A system comprising:

a data processor having an input data port and an output control port;

a memory having a data port to provide output data;

a bit access controller having an input data port coupled to the output data port of the memory, an input control port coupled to the output control port and an output data port coupled to the input data port of the data processor, the bit access controller further including;

a plurality of line storage locations coupled to the input data port of the bit access controller, wherein each line storage location stores data having N bit locations including a first bit and a last bit; and

a bit shift module having an input port coupled to the plurality of line storage locations and an output port coupled to the input data port of the data processor, the bit shift module to provide at the output port shifted bit values that are shifted relative to their storage location within the plurality of line storage locations.

2. The system of claim 1, wherein the plurality of storage locations are part of a circular buffer.

3. The system of claim 2, wherein the circular buffer is used to form a first-in, first-out (FIFO) buffer.

4. The system of claim 1, wherein the plurality of storage locations are part of a first-in, first-out (FIFO) buffer.

5. The system of claim 1, further comprising a memory control portion having a first control port coupled to a control port of the bit manipulator and a second control port coupled to a control port of the memory, wherein the memory control portion requests data from memory to be stored in the plurality of line storage locations.

6. The system of claim 5, further comprising a watermark storage location to store a value to indicate the memory control portion is to request data from memory.

7. The system of claim 1, wherein the data processor further comprises a general purpose processor.

8. The system of claim 7, wherein the general purpose processor includes a RISC type processor.

9. The system of claim 8, wherein the RISC type processor includes a MIPs based processor.

10. The system of claim 9, further comprising a video processor, wherein the video processor is separate from the data processor.

11. The system of claim 9, wherein the video processor includes a video transcoder.

12. The system of claim 1, further comprising a storage location coupled to the bit access controller to store a value indicating an amount of valid data stored in the plurality of line storage locations.

13. The system of claim 1, wherein the bit access controller further includes an interrupt output coupled to an input of the data processor, where the interrupt output is to be asserted by the bit access controller each time a predetermined number of line storage locations of the plurality of line storage locations is accessed.

14. The system of claim 13, wherein a line storage location is accessed when it is loaded with data.

15. The system of claim 13, wherein a line storage location is accessed when its data is read.

16. The system of claim 1, wherein the shifted bit values are shifted based on a value received at the input control port.