Stream processor

• US 7,054,989 B2
• Filed: 08/02/2002
• Issued: 05/30/2006
• Est. Priority Date: 08/06/2001
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Mizobata, Norihiko
• Primary Examiner(s): Shin, Christopher B.
• Application Number:
  US10/210,096
• Publication Number:
  US 20030028791A1
• Time in Patent Office: 1,397 Days
• Field of Search: 710 29- 38, 710305-317, 375/240.T
• US Class Current: 710/316
• CPC Class Codes: H04N 5/765 Interface circuits between an apparatus for recording and another apparatus
• CPC Class Codes: H04N 5/775 between a recording apparatus and a television receiver

Abstract

The stream processor of the present invention includes: a selection section and first to fifth processing sections. In the selection section, a plurality of inputs are associated with a plurality of outputs according to control from outside so that streams sent to the plurality of inputs are passed to the associated outputs. The first processing section sends a first stream to the first input among the plurality of inputs. The second processing section sends a second stream to the second input among the plurality of inputs. The third processing section receives a stream from the first output among the plurality of outputs. The fourth processing section receives a stream from the second output among the plurality of outputs. The fifth processing section receives a stream from the third output among the plurality of outputs, subjects the received stream to predetermined processing, and sends the processed stream to the third input among the plurality of inputs.

Claims

1. A stream processor comprising:

a selection section having a plurality of inputs associated with a plurality of outputs according to control from outside so that streams sent to the plurality of inputs are passed to the associated outputs;

a first processing section for sending a first stream to the first input among the plurality of inputs;

a second processing section for sending a second stream to the second input among the plurality of inputs;

a third processing section for receiving a stream from the first output among the plurality of outputs;

a fourth processing section for receiving a stream from the second output among the plurality of outputs; and

a fifth processing section for receiving a stream from the third output among the plurality of outputs, subjecting the received stream to predetermined processing, and sending the processed stream to the third input among the plurality of inputs.

2. The stream processor of claim 1, wherein the selection section associates the plurality of inputs with the plurality of outputs in one-to-one relationship.

3. The stream processor of claim 1, wherein the selection section associates one input among the plurality of inputs with two outputs among the plurality of outputs.

4. The stream processor of claim 2, wherein the selection section multiplexes at least two outputs among the plurality of outputs to obtain one new output.

5. The stream processor of claim 3, wherein the selection section multiplexes at least two outputs among the plurality of outputs to obtain one new output.

6. The stream processor of claim 1, wherein the fifth processing section retrieves desired information from the received stream to generate a partial stream and sends the generated partial stream to the third input among the plurality of inputs.

7. The stream processor of claim 1, wherein at least one of the third processing section and the fourth processing section outputs the received stream after change of the interface format of the stream.

8. The stream processor of claim 1, wherein at least one of the first stream and the second stream includes video data and/or audio data, and

at least one of the third processing section and the fourth processing section decodes the video data and/or the audio data included in the received stream.

9. The stream processor of claim 8, wherein the fifth processing section retrieves desired video data and/or audio data from the received stream and sends the retrieved video data and/or audio data to the third input among the plurality of inputs.

10. The stream processor of claim 1, wherein at least one of the first stream and the second stream has been encrypted, and

the fifth processing section decrypts the received stream.

11. The stream processor of claim 1, wherein the fifth processing section encrypts the received stream.

12. The stream processor of claim 10, wherein at least one of the first stream and the second stream has been encrypted according to a first encryption scheme,

the stream processor further comprises a sixth processing section, and

the sixth processing section receives a stream from the fourth output among the plurality of outputs, encrypts the received stream according to a second encryption scheme, and sends the encrypted stream, which is encrypted according to the second encryption scheme, to the fourth input among the plurality of inputs.

13. The stream processor of claim 1, further comprising a memory section,

at least one of the third processing section and the fourth processing section writes the received stream into the memory section,

at least one of the first processing section and the second processing section reads a stream from the memory section and gives the read stream to the associated input.

14. The stream processor of claim 13, wherein at least one of the third processing section and the fourth processing section memorizes the write position in the memory section of the stream written in the memory section, and

at least one of the first processing section and the second processing section memorizes the read position in the memory section of the stream read from the memory section.

15. The stream processor of claim 14, wherein at least one of the first processing section and the second processing section reads the stream from the memory section by referring to the write position memorized in at least one of the third processing section and the fourth processing section.

16. The stream processor of claim 14, wherein at least one of the third processing section and the fourth processing section writes the stream in a region of the memory section other than a region in which an unread stream is stored by referring to the read position memorized by at least one of the first processing section and the second processing section.

17. The stream processor of claim 13, wherein at least one of the first stream and the second stream includes a plurality of packets,

each of the plurality of packets includes identification information indicating the type of data contained in the packet,

the fifth processing section retrieves a desired packet from the plurality of packets included in the received stream by referring to the identification information to generate a first partial stream, and sends the first partial stream to the third input among the plurality of inputs,

the selection section is associated such that the first partial stream input from the third input is output from the first output,

the third processing section writes the received first partial stream into the memory section,

at least one of the first processing section and the second processing section reads the first partial stream from the memory section and sends the read first partial stream to the associated input as a second partial stream,

the selection section is associated such that the second partial stream input from the associated input is output from the second output, and

the fourth processing section extracts desired information from the received second partial stream.