Synchronous flash memory with non-volatile mode register
First Claim
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1. A synchronous non-volatile memory comprising:
- an array of non-volatile memory cells;
a memory controller;
a non-volatile mode register having a plurality of bit locations to store pre-determined mode data; and
a volatile mode register coupled in parallel with the non-volatile mode register to receive a copy of the mode data from the non-volatile mode register, the memory controller coupled to the volatile mode register and wherein the memory controller establishes operating settings in response to the mode data in the volatile mode register.
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Abstract
A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The memory device performs memory access operations using mode data that can be stored in a non-volatile mode register. The mode data can be copied into a volatile mode register. Both the non-volatile and volatile mode register can be edited during operation.
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Citations
23 Claims
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1. A synchronous non-volatile memory comprising:
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an array of non-volatile memory cells; a memory controller; a non-volatile mode register having a plurality of bit locations to store pre-determined mode data; and a volatile mode register coupled in parallel with the non-volatile mode register to receive a copy of the mode data from the non-volatile mode register, the memory controller coupled to the volatile mode register and wherein the memory controller establishes operating settings in response to the mode data in the volatile mode register. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method of operating a synchronous non-volatile memory device comprising:
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copying mode data from a non-volatile mode register to a volatile mode register prior to accessing the memory device; initiating a data access operation; reading the mode data from the volatile mode register; and controlling the data access operation in response to the mode data. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16)
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17. A processing system, comprising:
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a processor; and a synchronous non-volatile memory coupled to the processor and comprising; an array of non-volatile memory cells; a memory controller; a non-volatile mode register having a plurality of bit locations to store pre-determined mode data; and a volatile mode register coupled in parallel with the non-volatile mode register to receive a copy of the mode data from the non-volatile mode register, the memory controller coupled to the volatile mode register and wherein the memory controller establishes operating settings in response to the mode data in the volatile mode register. - View Dependent Claims (18, 19, 20, 21, 22, 23)
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Specification