Data cache scrub mechanism for large L2/L3 data cache structures

• US 7,055,003 B2
• Filed: 04/25/2003
• Issued: 05/30/2006
• Est. Priority Date: 04/25/2003
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Reick, Kevin Franklin, Guthrie, Guy Lynn, Cargnoni, Robert Alan, Helterhoff, Harmony Lynn
• Primary Examiner(s): Elmore, Reba I.
• Application Number:
  US10/424,528
• Publication Number:
  US 20040215886A1
• Time in Patent Office: 1,131 Days
• Field of Search: 711/122, 711/124, 711/134, 711/135
• US Class Current: 711/135
• CPC Class Codes: G06F 11/106 Correcting systematically all correctable errors, i.e. scrubbing
• CPC Class Codes: G06F 11/1064 in cache or content addressable memories
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0891 using clearing, invalidating or resetting means
• CPC Class Codes: G06F 12/126 with special data handling, e.g. priority of data or instructions, handling errors or pinning

Abstract

A method of reducing errors in a cache memory of a computer system (e.g., an L2 cache) by periodically issuing a series of purge commands to the L2 cache, sequentially flushing cache lines from the L2 cache to an L3 cache in response to the purge commands, and correcting errors (single-bit) in the cache lines as they are flushed to the L3 cache. Purge commands are issued only when the processor cores associated with the L2 cache have an idle cycle available in a store pipe to the cache. The flush rate of the purge commands can be programmably set, and the purge mechanism can be implemented either in software running on the computer system, or in hardware integrated with the L2 cache. In the case of the software, the purge mechanism can be incorporated into the operating system. In the case of hardware, a purge engine can be provided which advantageously utilizes the store pipe that is provided between the L1 and L2 caches. The L2 cache can be forced to victimize cache lines, by setting tag bits for the cache lines to a value that misses in the L2 cache (e.g., cache-inhibited space). With the eviction mechanism of the cache placed in a direct-mapped mode, the address misses will result in eviction of the cache lines, thereby flushing them to the L3 cache.

Claims

1. A method of reducing double-bit errors in a cache memory of a computer system, comprising the steps of:

periodically issuing a series of purge commands to the cache memory;

sequentially flushing cache lines from the cache memory to a lower level memory device of the computer system in response to said issuing step to eventually flush all cache lines from the cache memory; and

correcting errors in the cache lines as they are flushed to the lower level memory device.

2. The method of claim 1 wherein said issuing step is performed in response to the further step of determining that one or more processor cores associated with the cache memory have an idle cycle available in a store pipe to the cache memory.

3. The method of claim 1 wherein said correcting step corrects only single-bit errors in the cache lines.

4. The method of claim 1, further comprising the step of programmably setting a flush rate for said issuing step.

5. The method of claim 1 wherein said issuing step is carried out by software running on the computer system.

6. The method of claim 5 wherein:

the software carrying out said issuing step is an operating system of the computer system; and

said issuing step is performed in response to the further step of the operating system monitoring CPU usage to determine that one or more processing cores of the computer system have an idle cycle available in a store pipe to the cache memory.

7. The method of claim 1 wherein said issuing step is carried out by hardware integrated with the cache memory.

8. The method of claim 7, further comprising the step of programmably triggering the hardware to issue the purge commands.

9. A purge mechanism for a cache memory of a computer system, comprising:

means for periodically issuing a series of purge commands to the cache memory;

means for sequentially flushing cache lines from the cache memory to a lower level memory device of the computer system in response to said issuing means to eventually flush all cache lines from the cache memory; and

means for correcting errors in the cache lines as they are flushed to the lower level memory device.

10. The purge mechanism of claim 9 wherein said issuing means determines that one or more processor cores associated with the cache memory have an idle cycle available in a store pipe to the cache memory.

11. The purge mechanism of claim 9 wherein said correcting means corrects only single-bit errors in the cache lines.

12. The purge mechanism of claim 9 wherein said issuing means programmably sets a flush rate for the purge commands.

13. The purge mechanism of claim 9 wherein said issuing means is implemented in software running on the computer system.

14. The purge mechanism of claim 13 wherein:

said software is an operating system of the computer system; and

said operating system monitors CPU usage to determine that one or more processing cores of the computer system have an idle cycle available in a store pipe to the cache memory.

15. The purge mechanism of claim 9 wherein said issuing means is implemented in hardware integrated with the cache memory.

16. The purge mechanism of claim 15 wherein said hardware is programmably triggered to issue the purge commands.

17. A computer system comprising:

one or more processing cores;

a main memory device;

at least one cache memory connected to said one or more processing cores and said main memory device;

a purge mechanism which periodically issues a series of purge commands that sequentially flush cache lines from said cache memory to a lower level memory device of the computer system to eventually flush all cache lines from the cache memory; and

error correction code (ECC) logic which corrects errors in the cache lines as they are flushed to said lower level memory device.

18. The computer system of claim 17 wherein said purge mechanism issues the purge commands only when said one or more processor cores have an idle cycle available in a store pipe to said cache memory.

19. The computer system of claim 17 wherein said ECC logic corrects only single-bit errors in the cache lines.

20. The computer system of claim 17 wherein said purge mechanism has a programmable flush rate for the purge commands.

21. The computer system of claim 17 wherein said purge mechanism is implemented in software running on the computer system.

22. The computer system of claim 21 wherein:

said software is an operating system of the computer system; and

said operating system monitors CPU usage to determine that said one or more processing cores have an idle cycle available in a store pipe to said cache memory.

23. The computer system of claim 17 wherein said purge mechanism is implemented in a hardware purge engine integrated with the cache memory.

24. The computer system of claim 23 wherein said purge engine is programmably triggered to issue the purge commands.