System and method for evaluating signal deviations in a package design

• US 7,055,124 B2
• Filed: 02/19/2003
• Issued: 05/30/2006
• Est. Priority Date: 02/19/2003
• Status: Expired due to Fees

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Quint, David W., Frank, Mark D., Nelson, Jerimy
• Primary Examiner(s): Siek, Vuthe
• Assistant Examiner(s): TAT, BINH C
• Application Number:
  US10/368,758
• Publication Number:
  US 20040162714A1
• Time in Patent Office: 1,196 Days
• Field of Search: 716 4- 6, 716 16- 18, 716/1, 716/13
• US Class Current: 716/112
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A method is provided for evaluating signal deviations in an electronic design (e.g., a package design), including the steps of: formulating one or more signal deviation rules; processing the electronic design to determine whether the signal deviations violate the signal deviation rules; and generating an indicator (e.g., a DRC and/or report) associated with the electronic design to identify violated signal deviation rules. Processing of the electronic design may be scoped according one or a group of signal nets.

Claims

1. A method for evaluating signal deviations in an electronic design, comprising the steps of:

formulating one or more signal deviation rules;

processing the electronic design to determine whether the signal deviations of the electronic design violate the signal deviation rules; and

generating an indicator associated with the electronic design to identify violated signal deviation rules.

2. A method of claim 1, the step of processing comprising the step of processing one signal net of the electronic design for violation of the signal deviation rules.

3. A method of claim 1, the electronic design comprising a package design, the step of formulating comprising the step of formulating one or more group signal deviation rules for a group of signal nets of the package design, wherein the step of processing comprises the step of processing the group of signal nets to determine whether signal deviations of the group of signal nets violate the group signal deviation rules.

4. A method of claim 3, the step of generating comprising the step of generating at least one DRC for one or more violations of the group signal deviation rules.

5. A method of claim 3, wherein the step of processing the group of signal nets comprises the steps of determining a mean number of signal deviations for the signal nets within the group, and then evaluating each signal net in the group as to whether each signal net violates the group signal deviation rules.

6. A method of claim 5, further comprising the step of determining whether each other signal net has more or less than two signal deviations from the mean number.

7. A method of claim 3, the group signal deviation rules defining that no signal net within the group may have more or less than X signal deviations as compared to any other signal net within the group, X being an integer greater than or equal to one.

8. A method of claim 3, the group signal deviation rules defining that no signal net within the group may have more than Y signal deviations, Y being an integer greater than or equal to 1.

9. A method of claim 1, the step of generating an indicator comprising the step of graphically depicting a DRC on a graphical user interface illustrating the electronic design.

10. A method of claim 1, the step of processing comprising determining a number of signal deviations within one or more signal nets of the electronic design.

11. A method of claim 1, the electronic design comprising a package design, the signal deviation rules defining that signal nets carrying clocking signals cannot have more than Y signal deviations, the step of processing comprising the step of determining whether any signal net carrying a clocking signal violates Y signal deviations.

12. A method of claim 11, Y is two.

13. A method of claim 1, the step of generating an indicator comprising generating a report summarizing violations of the signal deviation rules.

14. A software product comprising instructions, stored on computer-readable media, wherein the instructions, when executed by a computer, perform steps for determining signal deviations in an electronic design, comprising:

instructions for determining instances of signal deviations within the electronic design;

instructions for comparing the instances to one or more signal deviation rules; and

instructions for generating an indicator associated with the electronic design to identify violations of the signal deviation rules.

15. The software product of claim 14, further comprising instructions for formulating one or more of the signal deviation rules.

16. The software product of claim 14, further comprising instructions for determining whether one signal net in a group of signal nets exceeds a threshold of signal deviations.

17. The software product of claim 14, further comprising instructions for generating a report summarizing violations of the signal deviation rules.

18. The software product of claim 14, further comprising instructions for counting signal deviations within the electronic design.

19. The software product of claim 14, further comprising instructions for responding to designer inputs to scope the step of determining instances of signal deviations.

20. A system for evaluating signal deviations in an electronic design, comprising:

means for formulating one or more signal deviation rules;

means for processing the electronic design to determine whether the signal deviations of the electronic design violate the signal deviation rules; and

means for generating an indicator associated with the electronic design to identify violated signal deviation rules.