DRAM cell having MOS capacitor and method for manufacturing the same

• US 7,056,790 B2
• Filed: 12/16/2003
• Issued: 06/06/2006
• Est. Priority Date: 12/16/2002
• Status: Expired due to Fees

• Current Assignee: Chung Cheng Holdings LLC (Intellectual Ventures LLC)
• Original Assignee: Icheon-Shi
• Inventors: Kim, Hak-yun
• Primary Examiner(s): Le, Thao P.
• Application Number:
  US10/737,052
• Publication Number:
  US 20040126970A1
• Time in Patent Office: 903 Days
• Field of Search: 438/257, 438/243, 257/301
• US Class Current: 438/257
• CPC Class Codes: H10B 12/038 the capacitor being in a trench in the substrate
• CPC Class Codes: H10B 12/0385 Making a connection between the transistor and the capacitor, e.g. buried strap
• CPC Class Codes: H10B 12/0387 Making the trench
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells

Abstract

A DRAM cell having a MOS capacitor and a method for manufacturing the same are disclosed. The DRAM cell includes: an active region of a semiconductor substrate; a MOS capacitor consisting of a plate node electrode which is a part of the active region, a storage node electrode having a T-shaped structure through a trench of the active region and an insulator thin film formed between the plate node electrode and the storage node electrode; a cell transistor having a gate insulating film and a gate electrode which are formed on the top surface of the active region and a source/drain formed within the active region; an interlayer insulating film deposited on a structure with the MOS capacitor and the cell transistor; a contact electrode connected with the source/drain of the cell transistor or with the storage node electrode of the MOS capacitor through a contact hole of the interlayer insulating film; a wire connected with the drain and the storage node electrode through the contact electrode; and a bit line connected with the source through the contact electrode.

Claims

1. A method for manufacturing a DRAM cell, the method comprising:

forming a trench in an active region of a semiconductor substrate;

implanting impurities into the active region;

forming an insulator thin film and a gate insulating film simultaneously on the substrate and the trench;

forming a storage node electrode of a MOS capacitor having a T-shaped structure and a gate electrode of a cell transistor simultaneously by depositing a conductive film on the insulator thin film and the trench to bury the trench and then patterning the conductive film;

forming a source/drain of the cell transistor by implanting impurities into the resulting material;

forming a contact electrode connected to the source/drain of the cell transistor or to the storage node electrode of the MOS capacitor by forming an interlayer insulating film on the whole surface of the resulting material, forming a contact hole on the interlayer insulating film and then burying the conductive film into the contact hole; and

forming a wire connected with the drain and the storage node electrode and a bit line connected with the source through the contact electrode by depositing a conductive film on top of the interlayer insulating film and patterning the same.

2. The method of claim 1, wherein the trench of the MOS capacitor comprises a plurality of curved trenches joined together by at least one linking trench.

3. The method of claim 1, wherein a gap-fill layer is further formed for filling the lower part of the trench with an insulating material before implanting impurities into the active region.

4. The method of claim 3, wherein the gap-fill layer is formed on the trench of the storage node region of the MOS capacitor or on the trench of the device isolation region of the semiconductor substrate.

5. The method of claim 4, wherein the gap-fill layer formed on the trench of the storage node region of the MOS capacitor is buried down to a top surface of the trench or a predetermined portion thereof.

6. The method of claim 1, wherein a side wall spacer is additionally formed on the side walls of the storage node electrode of the MOS capacitor and on the side walls of the gate electrode of the cell transistor before the forming the source/drain of the cell transistor.

7. The method of claim 1, wherein a power line is additionally formed for supplying a power voltage to the plate node electrode via another contact electrode of the interlayer insulating film during the step of depositing a conductive film on top of the interlayer insulating film and patterning the same.