Thin-film transistor used as heating element for microreaction chamber

• US 7,056,795 B2
• Filed: 01/03/2005
• Issued: 06/06/2006
• Est. Priority Date: 12/20/2001
• Status: Expired due to Term

• Current Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: Bryant, Frank R.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Lee, Calvin
• Application Number:
  US11/028,985
• Publication Number:
  US 20050136598A1
• Time in Patent Office: 519 Days
• Field of Search: 257/510, 257/519, 257/777, 347 9- 24, 438/21, 438/54, 438/282, 438/292, 438/351, 438381-385
• US Class Current: 438/292
• CPC Class Codes: B01J 19/0093 Microreactors, e.g. miniaturised or microfabricated reactors laboratory containers with capillary fluid transport in microfabricated channels or chambers B01L3/5027
• CPC Class Codes: B01J 2219/00783 Laminate assemblies, i.e. the reactor comprising a stack of plates
• CPC Class Codes: B01J 2219/00828 Silicon wafers or plates
• CPC Class Codes: B01J 2219/00853 Employing electrode arrangements
• CPC Class Codes: B01J 2219/00873 Heat exchange
• CPC Class Codes: B01L 3/5027 by integrated microfluidic structures, i.e. dimensions of channels and chambers are such that surface tension forces are important, e.g. lab-on-a-chip B01L3/5023 takes precedence; micromixers B01F33/30; microreactors for synthesis B01J19/0093; microcapillary devices in general B81B1/00
• CPC Class Codes: B41J 2/14129 Layer structure
• CPC Class Codes: F24V 99/00 Subject matter not provided for in other main groups of this subclass
• CPC Class Codes: G01N 2035/00376 Conductive heating, e.g. heated plates
• CPC Class Codes: G01N 25/4826 concerning the heating or cooling arrangements heating apparatus for chemical or physical laboratory apparatus in general B01L7/00
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78624 the source and the drain regions being asymmetrical
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H05B 2203/013 Heaters using resistive films or coatings
• CPC Class Codes: H05B 2203/017 Manufacturing methods or apparatus for heaters
• CPC Class Codes: H05B 3/26 heating conductor mounted on insulating base for transparent areas H05B3/84, H05B3/86

Abstract

The thin film transistor formed of polycrystalline silicon is positioned adjacent a heat reaction chamber. The gate electrode for the transistor is formed within a silicon substrate and a gate dielectric is positioned over the gate electrode. A pass transistor is coupled to the gate electrode, the pass transistor having a source/drain region in the same semiconductor substrate and positioned adjacent to the gate electrode of the thin film heating transistor. When the pass transistor is enabled, a voltage is applied to the gate electrode which causes the current to flow from the drain to the source of the thin film transistor. The current flow passes through a highly resistive region which generates heat that is transmitted to the heat reaction chamber.

Claims

1. A method of making a semiconductor heater assembly, comprising:

forming electrically insulating regions within a semiconductor substrate;

forming a gate electrode of a transistor within the semiconductor substrate;

forming a gate dielectric over the gate electrode;

forming source, drain, and channel regions of the transistor with the channel region positioned over the gate dielectric; and

forming a microreaction chamber over the channel region of the transistor.

2. The method of claim 1, comprising:

Forming, in the substrate, a pass transistor having a conduction terminal in electrical contact with the gate, the pass transistor configured to regulate heat-generating current in the channel region of the transistor.

3. The method of claim 1 wherein forming the microreaction chamber comprises:

depositing a photoreactive layer over the channel region;

depositing an additional layer on the photoreactive layer; and

exposing the photoreactive layer to light to define the microreaction chamber.

4. The method of claim 3 wherein the exposing step is performed after depositing the additional layer.

5. A method of making a semiconductor heater assembly, comprising:

forming electrically insulating regions within a semiconductor substrate;

forming a gate electrode within the semiconductor substrate;

forming a gate dielectric over the gate electrode and located between the insulating regions;

forming a layer of polycrystalline silicon overlying the insulating regions and the gate dielectric;

doping source and drain regions within the polycrystalline silicon layer to have a selected low resistivity to obtain a thin-film transistor;

forming a heat responsive reaction chamber over the polycrystalline silicon layer.

6. The method according to claim 5, further including:

doping a region within the polycrystalline silicon layer to form a resistive region having a selected resistivity.

7. The method according to claim 6 wherein the resistive region is the same conductivity type as the source and drain regions within the polycrystalline silicon layer.

8. The method according to claim 6 wherein the resistive region is a different conductivity type as the source and drain regions within the polycrystalline silicon layer.

9. The method according to claim 6 wherein the resistive region is coextensive with the heat responsive reaction chamber.

10. The method according to claim 6 wherein the resistive region is smaller than the heat responsive reaction chamber.

11. The method according to claim 5, further including:

forming source and drain regions of a pass transistor adjacent to the gate electrode simultaneously with forming the gate electrode in the substrate, using the same process steps and having the same conductivity type.

12. The method according to claim 11, further including:

forming a second gate dielectric for the pass transistor prior to forming the gate dielectric of the thin-film transistor.