Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor
First Claim
1. A memory device comprising:
- a substrate;
a plurality of memory cells, each of the memory cells including capacitor, and a transistor formed vertically from the substrate, the transistor including a first source/drain region, a body region, and a second source/drain region, the capacitor including a first capacitor plate integral with the second source/drain region, and a second capacitor plate separate from the first capacitor plate;
a metal contact for providing an ohmic contact for the second capacitor plate on a surface of the substrate;
a plurality of trenches dividing the memory cells into rows and columns, wherein the second capacitor plate of the capacitor of each of the memory cells is formed in the trenches;
a plurality of word lines for accessing the memory cells; and
a plurality of bit lines for exchanging data with the memory cells.
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Abstract
A memory cell for a memory array in a folded bit line configuration. The memory cell includes an access transistor formed in a pillar of single crystal semiconductor material. The access transistor has first and second source/drain regions and a body region that are vertically aligned. The access transistor further includes a gate coupled to a wordline disposed adjacent to the body region. The memory cell also includes a passing wordline that is separated from the gate by an insulator for coupling to other memory cells adjacent to the memory cell. The memory cell also includes a trench capacitor. The trench capacitor includes a first plate that is formed integral with the first source/drain region of the access transistor. The trench capacitor also includes a second plate that is disposed adjacent to the first plate and separated from the first plate by a gate oxide.
207 Citations
42 Claims
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1. A memory device comprising:
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a substrate; a plurality of memory cells, each of the memory cells including capacitor, and a transistor formed vertically from the substrate, the transistor including a first source/drain region, a body region, and a second source/drain region, the capacitor including a first capacitor plate integral with the second source/drain region, and a second capacitor plate separate from the first capacitor plate; a metal contact for providing an ohmic contact for the second capacitor plate on a surface of the substrate; a plurality of trenches dividing the memory cells into rows and columns, wherein the second capacitor plate of the capacitor of each of the memory cells is formed in the trenches; a plurality of word lines for accessing the memory cells; and a plurality of bit lines for exchanging data with the memory cells. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A memory device comprising:
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a plurality of pillars, each of the pillars including a number of regions formed outwardly from a substrate, the regions including a first source/drain region, a body region, and a second source/drain region; a plurality of trenches dividing the pillars into columns and rows in which each of the columns includes a number of pillars and each of the rows includes a number of pillars, a plurality of word line pairs, each of the word line pairs being formed in one of the trenches parallel with the rows, each of the word line pairs including a first word line and a second word line, the first word line including gate portions, each of the gate portions being disposed across from the body region of each of the pillars in a first group of columns, the second word line including gate portions, each of the gate portions of the second word line disposed across from the body region of each of the pillars in a second group of columns; a plurality of bit lines, each of the bit lines coupled to the first source/drain region of each of the pillars in one of the columns; a plurality of trench capacitors, each of the trench capacitors including a first capacitor plate and a second capacitor plate, the first capacitor plate being integral with the second source/drain region of one of the pillars, the second capacitor plate being separate from the first capacitor plate and surrounding at least a portion of the first capacitor plate; a metal contact for providing an ohmic contact for the second capacitor plate on a surface of the substrate. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24)
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25. A memory device comprising:
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a plurality of memory cells, each of the memory cells including a capacitor, and a transistor formed vertically from a substrate, the transistor including a first source/drain region, a body region, and a second source/drain region, the capacitor including a first capacitor plate integral with the second source/drain region and a second capacitor plate separate from the first capacitor plate and surrounding the first plate; a metal contact for providing an ohmic contact for the second capacitor plate on a surface of the substrate; a plurality of trenches dividing the memory cells into rows and columns, each of the trenches including an insulation layer lining a portion of each of the trenches and formed between the first and second capacitor plates of the capacitor of each of the memory cells; a plurality of word line pairs to access the memory cells, each of the word line pairs being formed in one of the trenches; and a plurality of bit lines, each of the bit lines being coupled to memory cells in one of the columns. - View Dependent Claims (26, 27)
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28. A memory device comprising:
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a plurality of memory cells, each of the memory cells including a capacitor, and a transistor formed vertically from a substrate, the transistor including a first source/drain region, a body region, and a second source/drain region, the capacitor including a first capacitor plate integral with the second source/drain region and a second capacitor plate separate from the first capacitor plate and surrounding the first plate; a metal contact coupling the second capacitor plate of the capacitor of each of the memory cells to the substrate; a plurality of trenches dividing the memory cells into rows and columns, each of the trenches including an insulation layer lining a portion of each of the trenches and formed between the first and second capacitor plates of the capacitor of each of the memory cells; a plurality of word line pairs to access the memory cells, each of the word line pairs being formed in one of the trenches; and a plurality of bit lines, each of the bit lines being coupled to memory cells in one of the columns. - View Dependent Claims (29, 30, 31, 32, 33, 34, 35)
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36. A system comprising:
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a processor; and a memory device coupled to the processor, the memory device including; a plurality of memory cells, each of the memory cells including a capacitor, and a transistor formed vertically from a substrate, the transistor including a first source/drain region, a body region, and a second source/drain region, the capacitor including a first capacitor plate integral with the second source/drain region and a second capacitor plate separate from the first capacitor plate; a metal contact for providing an ohmic contact for the second capacitor plate on a surface of the substrate; a plurality of trenches dividing the memory cells into rows and columns, wherein the second capacitor plate of each of the capacitors is formed in the trenches; a plurality of word lines configured for accessing the memory cells; and a plurality of bit lines configured for transferring data between the memory cells and the processor. - View Dependent Claims (37, 38, 39, 40, 41, 42)
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Specification