Mirror image memory cell transistor pairs featuring poly floating spacers

• US 7,057,235 B2
• Filed: 09/29/2004
• Issued: 06/06/2006
• Est. Priority Date: 04/25/2003
• Status: Expired due to Fees

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Inventors: Lojek, Bohumil
• Primary Examiner(s): Smith, Zandra V
• Assistant Examiner(s): Perkins, Pamela E
• Application Number:
  US10/955,453
• Publication Number:
  US 20050056882A1
• Time in Patent Office: 615 Days
• Field of Search: 257/66, 257/315, 257/321, 257/326, 257/331
• US Class Current: 257/326
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7887 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

By arranging floating spacer and gate non-volatile memory transistors in symmetric pairs, increased chip density may be attained. For each pair of such transistors, the floating gates are laterally aligned with floating spacers appearing on laterally outward edges of each floating gate. At laterally inward edges, the two transistors share a common drain electrode. The transistors are independent of each other except for the shared drain electrode. Tunnel oxide separated the floating spacer from the floating gate, but both the spacer and the gate are maintained at a common potential, thereby providing dual paths for charge exiting the tunnel oxide, as the charged is propelled by a programming voltage. The pairs of transistors can be aligned in columns with the direction of the columns orthogonal to the direction of the pairs, thereby forming a memory array.

Claims

1. A semiconductor multi-bit, non-volatile memory structure comprising:

a pair of side-by-side floating gate memory cell devices fabricated in a common doped semiconductor substrate, one device to the left and one device to the right of a common central substrate region, each device having at least one sidewall spacer facing a central polysilicon body, insulated from the substrate, with left and right edges, the left device having a floating polysilicon spacer separated from the central polysilicon body on the left edge by tunnel oxide and the right device having a floating polysilicon spacer separated from the associated central polysilicon body on the right edge by tunnel oxide, each device having a substrate doped region forming an electrode outwardly adjacent to each polysilicon spacer and a shared electrode in the common central substrate region and each device having a polysilicon connector connecting the central polysilicon body electrically and the facing polysilicon spacer, the two memory cells capable of independently storing two binary bits of data in the form of charge transferred to and from the connected floating polysilicon spacers and the central polysilicon body, both at a common potential, under the influence of a control electrode atop the central polysilicon body, communicating charge to and from the substrate; and

wherein said polysilicon connector is a polysilicon layer associated with each memory cell contacting each polysilicon spacer and a portion of the central polysilicon body, electrically placing the spacer and polysilicon body at a common electrical potential.

2. The memory structure of claim 1 wherein a second polysilicon layer is the control electrode atop each polysilicon spacer and a portion of the facing central polysilicon body and separated therefrom by an oxide layer, wherein voltage signals applied to the second polysilicon layer cause electrical charge to tunnel into the underlying polysilicon spacer and facing polysilicon body from a doped substrate region.

3. The memory structure of claim 1 wherein the pair of side-by-side floating gate memory cell devices are disposed between opposed isolation regions.

4. The memory structure of claim 1 wherein the pair of side-by-side floating gate memory cell devices are symmetrically disposed about the common central substrate doped region.

5. The memory structure of claim 1 wherein the floating gate memory cell devices are programmed and erased in the manner of two separate and distinct electrically erasable programmable read only memory cells.

6. The memory structure of claim 5 wherein the floating gate memory cell devices are in a memory array.

7. A semiconductor multi-bit, non-volatile memory structure comprising:

at least one column of pairs of symmetric side-by-side floating gate memory cell devices fabricated in a common doped semiconductor substrate, each device having on one side of a plane of symmetry a central polysilicon body with an adjacent polysilicon spacer separated therefrom by tunnel oxide, with a first electrode in the substrate beneath the polysilicon spacer, a second electrode in the substrate disposed between and shared by the polysilicon bodies of the side-by-side devices and a third electrode insulated from and atop the polysilicon bodies, the central polysilicon body electrically joined to the adjacent polysilicon spacer, each device independently storing electrical charge by command of the third electrode communicating charge to and from the substrate and into the central polysilicon bodies and adjacent polysilicon spacers; and

wherein said polysilicon connector is a polysilicon layer associated with each memory cell contacting each polysilicon spacer and a portion of the central polysilicon body, electrically placing the spacer and polysilicon body at a common electrical potential.

8. The memory structure of claim 7 wherein at least a portion of the tunnel oxide extends vertically between the central polysilicon body and the adjacent polysilicon spacer.

9. The memory structure of claim 7 wherein said side-by-side memory cell devices are orthogonal to the direction of said at least one column, thereby forming a memory array.