Cross point memory array with fast access time

• US 7,057,914 B2
• Filed: 07/01/2003
• Issued: 06/06/2006
• Est. Priority Date: 08/02/2002
• Status: Expired due to Fees

• Current Assignee: Unity Semiconductor Corporation (Rambus Inc.)
• Original Assignee: Unity Semiconductor Corporation (Rambus Inc.)
• Inventors: Hsia, Steve Kuo-Ren, Kinney, Wayne, Rinerson, Darrell, Longcor, Steven W., Chevallier, Christophe J., Ward, Edmond R.
• Primary Examiner(s): LE, VU ANH
• Application Number:
  US10/612,776
• Publication Number:
  US 20040160848A1
• Time in Patent Office: 1,071 Days
• Field of Search: 365/51, 365/53, 365/63, 365/185.05, 365/158
• US Class Current: 365/51
• CPC Class Codes: G11C 11/5685 using storage elements comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 2213/31 Material having complex metal oxide, e.g. perovskite structure
• CPC Class Codes: G11C 2213/77 Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used

Abstract

Cross point array with fast access time. A cross point array is driven by drivers on a semiconductor substrate. The drivers for either a single-layer cross point array or for the bottom layer of a stacked cross point array can be positioned to improve access time. Specifically, if the x-direction drivers are positioned in the middle of the x-direction conductive array lines and the y-direction drivers are positioned in the middle of the y-direction conductive array lines, the access time will be improved.

Claims

1. A device comprising:

a semiconductor substrate;

a stacked cross point array formed over the semiconductor substrate, the stacked cross point array having at least two layers of memory cells, each successive layer of memory cells being formed over the previous layer of memory cells; and

drivers that are formed on the semiconductor substrate, the drivers being in electrical communication with the stacked cross point array;

wherein the stacked cross point array has at least two separate access times, the fastest of which is associated with the layer of memory cells closest to the semiconductor substrate;

wherein placement of the drivers contribute to the access time associated with the layer of memory cells closest to the semiconductor substrate being the fastest access time.

2. The device of claim 1, wherein:

the stacked cross point array has only two separate access times.

7. The device of claim 1 wherein the memory cells are re-writable.

8. The device of claim 1 wherein the memory cells include conductive metal oxides.

3. A device comprising:

a stacked cross point having

a first x-direction conductive array line layer;

a first memory plug layer having a first access time, and positioned on top of the first x-direction conductive array line layer;

a first y-direction conductive array line layer on top of the first memory plug layer;

a second memory plug layer having a second access time, and positioned on top of the first y-direction conductive array line layer; and

a second x-direction conductive array line layer on top of the second memory plug layer;

a first x-direction driver set in electrical communication with the first x-direction conductive array line layer;

a y-direction driver set in electrical communication with the first y-direction conductive array line layer; and

a second x-direction driver set in electrical communication with the first x-direction conductive array line layer;

wherein the first access time is faster than the second access time; and

wherein placement of the first and second x-direction drivers contribute to the first access time being faster than the second access time.

4. The device of claim 3, wherein:

the memory plug layers exhibit a non-linear resistive characteristic.

5. The device of claim 4, wherein:

the memory plugs include conductive metal oxides.

6. The device of claim 3, wherein:

the device is part of a re-writable memory.

9. The device of claim 3 wherein:

the first x-direction conductive array line layer includes a plurality of x-direction conductive array lines, each x-direction conductive array line having a middle and two ends along the x-direction;

the first x-direction driver includes a plurality of individual x-direction drivers, each individual x-direction driver connected to the middle of an x-direction conductive array line;

the plurality of x-direction conductive array lines includes an array cut, the array cut being where two contiguous x-direction conductive array lines are spaced further apart than other contiguous x-direction conductive array lines;

the first y-direction conductive array line layer includes a plurality of y-direction conductive array lines, each y-direction conductive array line having a middle and two ends along the y-direction;

the first y-direction driver includes a plurality of individual y-direction drivers, each individual y-direction driver connected to the middle of a y-direction conductive array line through the array cut.