Nonvolatile semiconductor memory device

• US 7,057,922 B2
• Filed: 09/10/2004
• Issued: 06/06/2006
• Est. Priority Date: 09/12/2003
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Fukumoto, Katsumi
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US10/938,014
• Publication Number:
  US 20050122768A1
• Time in Patent Office: 634 Days
• Field of Search: 365/158, 365/171, 365/173, 365/185.03, 365/185.11, 365/185.18, 365/185.24, 365/185.29, 365/185.33
• US Class Current: 365/158
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/5685 using storage elements comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0071 Write using write potential applied to access device gate
• CPC Class Codes: G11C 2013/009 Write using potential difference applied between cell electrodes
• CPC Class Codes: G11C 2213/31 Material having complex metal oxide, e.g. perovskite structure
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor

Abstract

The present invention employs a memory cell structure in that one end of a variable resistance element (1) for storing information by change of electric resistance is connected to a source of a selection transistor (2) to form a memory cell (3) and, in a memory cell array (4), a drain of the selection transistor (2) is connected to a common bit line (BL) in a column direction, the other end of the variable resistance element (1) is connected to a source line (SL) and a gate of the selection transistor (2) is connected to a common word line (WL) in a row direction. In the memory cell structure, an operation of resetting data stored in the memory cell (3) is carried out for each of sectors including the plural memory cells (3) commonly connected to the source line (SL).

Claims

1. A nonvolatile semiconductor memory device comprising:

an array of nonvolatile memory cells arranged in both rows and columns; and

a combination of word lines and bit lines arranged to extend in the row and column directions respectively so that they can select one of or a group of the memory cells for operation, wherein

the memory cell has a variable resistance element, in which data is stored through a change in electric resistance, connected at one end to a source of a selection transistor,

the selection transistor is connected at a drain to the bit line extending commonly along the column direction and at a gate to the word line extending commonly along the row direction while the variable resistance element is connected at the other end to a source line in the memory cell array,

a write operation on the memory cell can be electrically executed by a predetermined voltage applied to the selected word line to turn the selection transistor conductive and a predetermined writing voltage or current applied between the selected bit line and the selected source line, and

the reset operation on the memory cell can be electrically executed on the sector-by-sector basis, each sector including the plurality of memory cells connected to the common source line, by a predetermined voltage applied to the selected word line to turn the selection transistor conductive and a predetermined resetting voltage or current applied between the selected bit line and the selected source line.

2. The nonvolatile semiconductor memory device according to claim 1, wherein

the reset operation is executed by a pulsed form of a predetermined resetting voltage or current applied to the selected source line while the selected bit line is fixed at a resetting potential.

3. The nonvolatile semiconductor memory device according to claim 1, wherein

the reset operation is executed by a pulsed form of the predetermined voltage applied to the selected word line while the selected bit line and the selected source line are fixed at their respective resetting potentials.

4. The nonvolatile semiconductor memory device according to claim 1, wherein

the sector is divided into sub-sectors, and

the reset operation is executed in a time-division manner for each sub-sector.

5. The nonvolatile semiconductor memory device according to claim 4, wherein

the sub-sector to be subjected to the reset operation is determined by selecting the bit line connected to the memory cell in the sub-sector.

6. The nonvolatile semiconductor memory device according to claim 5, wherein

the sub-sector to be subjected to the reset operation is determined by holding at the resetting potential the bit line connected to the memory cell in the sub-sector, whereby the bit line connected to the memory cell in the sub-sector will be at the floating state thus to allow no selection of the other sub-sectors.

7. The nonvolatile semiconductor memory device according to claim 4, wherein

the reset operation is intended to lower the electric resistance of the memory cell, and

the resistance value of the memory cell in the sub-sector to be subjected to a time-division manner of the reset operation is controlled to stay not lower than a lower limit level.

8. The nonvolatile semiconductor memory device according to claim 1, wherein

the operation of lowering the electric resistance of the memory cell in the write operation or the reset operation is canceled when the resistance value of the memory cell is found lower than a reference level through comparison between the resistance value of the memory cell and the reference level during the action.

9. The nonvolatile semiconductor memory device according to claim 1, wherein

the reset operation is intended to lower the electric resistance of the memory cell, and

the reset operation is preceded by a verify operation for examining whether or not the resistance value of each memory cell to be subjected to the reset operation is lower than the predetermined reference level and when the every resistance value is lower than the reference level, the reset operation is not started.

10. The nonvolatile semiconductor memory device according to claim 1, wherein

the reset operation is intended to lower the electric resistance of the memory cell,

the reset operation is preceded by a first verify operation for examining whether or not the resistance value of each memory cell to be subjected to the reset operation is lower than a first reference level, and

when the every resistance value is lower than the first reference level, a second verify operation is conducted for examining whether or not the resistance value of the memory cell is higher than a second reference level and, when the every resistance value is higher than the second reference level, the reset operation is not started.

11. The nonvolatile semiconductor memory device according to claim 10, wherein

in the second verify operation, when at least one of the resistance values is not higher than the second reference level, the write operation is conducted on the memory cell of which the resistance value is not higher than the second reference level under a writing condition that the resistance value stays higher than the second reference level and lower than the first reference level.

12. The nonvolatile semiconductor memory device according to claim 1, wherein

the reset operation is intended to lower the electric resistance of the memory cell, and

the reset operation is preceded by the write operation for raising the resistance value of the memory cell to be subjected to the reset operation.

13. The nonvolatile semiconductor memory device according to claim 1, wherein

the write operation is intended to raise the electric resistance of the memory cell, and

the write operation is controlled so that it stops before the resistance value of the memory cell reaches a maximum during the write operation.

14. The nonvolatile semiconductor memory device according to claim 13, wherein

the resistance value of the memory cell during the write operation is compared with a write operation reference level predetermined to not higher than the maximum and the write operation is controlled to stop before the resistance value of the memory cell during the write operation reaches the maximum.

15. The nonvolatile semiconductor memory device according to claim 13, wherein

the resistance value of the memory cell during the write operation is compared with a write operation reference level predetermined to not higher than the maximum and the duration of time where the writing voltage is being applied or the number of applications of the writing voltage for allowing the resistance value of the memory cell during the write operation to reach the maximum is stored in an embedded nonvolatile memory area.

16. The nonvolatile semiconductor memory device according to claim 1, wherein

the write operation is intended to raise the electric resistance of the memory cell, and

the memory cells to be subjected to the write operation is divided into groups and the write operation is executed in a time-division manner for each group at least at the first application of the writing voltage.

17. The nonvolatile semiconductor memory device according to claim 16, wherein

as the write operation proceeds, the group is modified to increase the number of the memory cells in the group.

18. The nonvolatile semiconductor memory device according to claim 1, wherein

the write operation and the reset operation are executed in response to command data received at a predetermined input terminal or input/output terminal.

19. The nonvolatile semiconductor memory device according to claim 1, wherein

the write operation and the reset operation employ reference levels which are determined by the same variable resistance element as in the memory cell for verifying or comparing the resistance value of the memory cell.

20. The nonvolatile semiconductor memory device according to claim 1, further comprising:

a plurality of source terminals including dedicated source terminals for use with the write operation and the reset operation, wherein

the operating current received by the memory cell in the write operation or the reset operation is supplied from a source current through the dedicated terminal.

21. The nonvolatile semiconductor memory device according to claim 1, further comprising:

a bit line discharging circuit for connecting the bit line with a ground potential at the standby state where none of the read operation, the write operation, and the reset operation on the memory cell is conducted.

22. The nonvolatile semiconductor memory device according to claim 1, further comprising:

a comparator for comparing the resistance value of the memory cell with its reference level, the comparator connected at one of two inputs to a plurality of reference resistors via a reference resistance selecting circuit, the reference resistors providing reference levels for use with the read operation, the write operation, the reset operation, and a test on the memory cell; and

a reference resistance writing circuit for setting the reference resistors to predetermined resistance levels.

23. The nonvolatile semiconductor memory device according to claim 1, wherein

the memory cell is arranged to be at a data protection state where the write operation and the reset operation are inhibited at least for each sector.

24. The nonvolatile semiconductor memory device according to claim 1, wherein

the variable resistance element is fabricated using a CMR (Colossal Magneto-Resistive) layer or a TMR (Tunneling Magneto-Resistive) layer.

25. The nonvolatile semiconductor memory device according to claim 1, wherein

the variable resistance element is made of an oxide having a perovskite structure containing manganese.