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Erase verify for non-volatile memory

  • US 7,057,935 B2
  • Filed: 08/30/2001
  • Issued: 06/06/2006
  • Est. Priority Date: 08/30/2001
  • Status: Active Grant
First Claim
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1. A non-volatile memory comprising:

  • an array of non-volatile memory cells arranged in columns using bit lines; and

    a verify circuit selectively coupled to the bit lines to determine if the memory cells have an erase level that is within an erase level window defined by first and second reference signals, the circuit generating an indication of one of under-erasure, erasure, or over-erasure in response to a position of the erase level with the erase level window.

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