Erase verify for non-volatile memory
First Claim
1. A non-volatile memory comprising:
- an array of non-volatile memory cells arranged in columns using bit lines; and
a verify circuit selectively coupled to the bit lines to determine if the memory cells have an erase level that is within an erase level window defined by first and second reference signals, the circuit generating an indication of one of under-erasure, erasure, or over-erasure in response to a position of the erase level with the erase level window.
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Accused Products
Abstract
A memory device verify system determines a state of memory cells in a memory. The memory includes a memory array having a plurality of memory cells coupled to bit lines. A verify circuit is coupled to the bit lines to determine if memory cells have a erase level that is within predetermined upper and lower limits. The verify circuit can include first and second comparators. In one embodiment, the first comparator is used to compare a bit line current with an upper first reference current. The second comparator is used to compare a bit line current with a lower second reference current. The comparator circuit is not limited to reference currents, but can use reference voltages to compare to a bit line voltage. The verify circuit, therefore, eliminates the need for separate bit line leakage testing to identify over-erased memory cells. Memory verify methods using two reference signal are also provided.
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Citations
10 Claims
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1. A non-volatile memory comprising:
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an array of non-volatile memory cells arranged in columns using bit lines; and a verify circuit selectively coupled to the bit lines to determine if the memory cells have an erase level that is within an erase level window defined by first and second reference signals, the circuit generating an indication of one of under-erasure, erasure, or over-erasure in response to a position of the erase level with the erase level window. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A non-volatile memory comprising:
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an array of non-volatile memory cells arranged in a row and column format such that the columns comprise bit lines including a selected bit line having a bit line current; and a plurality of comparators for generating indication signals in response to a comparison of the bit line current with a plurality of reference currents each coupled to a comparator, each reference current indicating a different limit of an erase level window, each comparator generating an indication of one of under-erasure, erasure, or over-erasure in response to the comparison. - View Dependent Claims (9, 10)
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Specification