Method and apparatus for preventing undesirable packet download with pending read/write operations in data packet processing
First Claim
1. In a packet processor having a local packet memory (LPM) for storing packet data during processing, the LPM having a plurality of memory cells, the memory cells accessible by at least one memory access port, a system for managing port contention between at least two controllers that access the memory cells, comprising:
- a buffer for queuing write requests to the at least one memory port for a first one of the controllers; and
a logic mechanism associated with the buffer for determining whether a write request from said first one of the controllers is within said buffer and is directed at a first one of the memory cells, and if so, whether a read request exists from a second one of the controllers and is directed at said first one of the memory cells;
wherein, if a read request exists from said second one of the controllers and is directed at said first one of the memory cells while said write request is buffered, said read request is delayed until said write request has completed regardless of when said read request occurs.
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Accused Products
Abstract
A logic system for resolving port contentions associated with memory-access requests in data packet routing is provided. The logic system comprises a determination logic for assessing and reporting port status of busy or not busy, a command mechanism for issuing commands contingent on determination results and a staged buffer memory for holding pending requests waiting for permission to access the memory. A single request at the head of the buffer memory is considered for port access whereupon if a port is determined to be busy, the command logic issues appropriate commands to units responsible for downloading packets from the memory and for sending new memory-access requests.
106 Citations
10 Claims
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1. In a packet processor having a local packet memory (LPM) for storing packet data during processing, the LPM having a plurality of memory cells, the memory cells accessible by at least one memory access port, a system for managing port contention between at least two controllers that access the memory cells, comprising:
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a buffer for queuing write requests to the at least one memory port for a first one of the controllers; and a logic mechanism associated with the buffer for determining whether a write request from said first one of the controllers is within said buffer and is directed at a first one of the memory cells, and if so, whether a read request exists from a second one of the controllers and is directed at said first one of the memory cells; wherein, if a read request exists from said second one of the controllers and is directed at said first one of the memory cells while said write request is buffered, said read request is delayed until said write request has completed regardless of when said read request occurs. - View Dependent Claims (2, 3, 4, 5, 6)
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7. In a packet processor having a local packet memory (LPM) for storing packet data during processing, the LPM having a plurality of memory cells accessible by at least one access port, a method for managing contention between at least two controllers that access the memory cells, comprising the steps of:
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queuing write requests from a first controller to the port in a buffer; and determining, by a logic mechanism associated with the buffer, whether a write request from the first one of the controllers is within the buffer and is directed at a first one of the memory cells, and if so; determining whether a read request exists from a second one of the controllers and is directed at the first one of the memory cells; and if a read request exists from the second one of the controllers and is directed at the first one of the memory cells while the write request is buffered, delaying the read request until said write request has completed, regardless of when said read request occurs. - View Dependent Claims (8, 9, 10)
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Specification