Method of monitoring and/or controlling a semiconductor manufacturing apparatus and a system therefor

• US 7,058,470 B2
• Filed: 11/30/2004
• Issued: 06/06/2006
• Est. Priority Date: 09/06/2001
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Tanaka, Junichi, Shiraishi, Daisuke, Ikuhara, Shoji, Yamamoto, Hideyuki, Kitsunai, Hiroyuki, Masuda, Toshio, Kagoshima, Akira
• Primary Examiner(s): Picard, Leo
• Assistant Examiner(s): JARRETT, RYAN A
• Application Number:
  US10/999,006
• Publication Number:
  US 20050087298A1
• Time in Patent Office: 553 Days
• Field of Search: 700/29, 700/44, 700/45, 700108-110, 700/121
• US Class Current: 700/121
• CPC Class Codes: G05B 13/048 using a predictor
• CPC Class Codes: G05B 19/41865 characterised by job scheduling, process planning, material flow
• CPC Class Codes: G05B 2219/31357 Observer based fault detection, use model
• CPC Class Codes: G05B 2219/32058 Execute program as function of deviation from predicted state, result
• CPC Class Codes: G05B 23/024 Quantitative history assessment, e.g. mathematical relationships between available data; Functions therefor; Principal component analysis [PCA]; Partial least square [PLS]; Statistical classifiers, e.g. Bayesian networks, linear regression or correlation analysis; Neural networks
• CPC Class Codes: H01L 21/67276 Production flow monitoring, e.g. for increasing throughput program-control systems per se G05B19/00, e.g. total factory control G05B19/418
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

A semiconductor processing apparatus for processing a semiconductor wafer includes a sensor for monitoring a processing state of the semiconductor processing apparatus, a processing result input unit which inputs measured values for processing results of a semiconductor wafer processed by the semiconductor processing apparatus, and a model equation generation unit relying on sensed data acquired by the sensor and the measured values to generate a model equation for predicting a processing result using the sensed data as an explanatory variable. The apparatus includes a processing result prediction unit which predicts a processing result based on the model equation and the sensed data, and a process recipe control unit which compares the predicted processing result with a previously set value to control a processing condition or input parameter. The process recipe control unit includes a controller which controls at least one of a plurality of different processing performances for processing of the semiconductor wafer.

Claims

1. A semiconductor processing apparatus for processing a semiconductor wafer, comprising:

a sensor for monitoring a processing state of said semiconductor processing apparatus;

a processing result input unit which inputs measured values for processing results of a semiconductor wafer processed by said semiconductor processing apparatus;

a model equation generation unit relying on sensed data acquired by said sensor and said measured values to generate a model equation for predicting a processing result using said sensed data as an explanatory variable;

a processing result prediction unit which predicts a processing result based on said model equation and said sensed data; and

a process recipe control unit which compares said predicted processing result with a previously set value to control a processing condition of said semiconductor processing apparatus such that a deviation between said predicted processing result and said previously set value is corrected,

wherein said process recipe control unit includes a controller which controls at least one of a plurality of different processing performances for the processing of the semiconductor wafer without effecting change of others of the plurality of different processing performances.

2. A semiconductor processing apparatus for processing a semiconductor wafer according to claim 1, wherein said model equation unit generates the model equation using a partial least square (PLS) method.

3. A semiconductor processing apparatus for processing a semiconductor wafer according to claim 1, wherein said model equation unit generates the model equation using robust regression for measured data in which any abnormal measured data is removed.

4. A semiconductor processing apparatus for processing a semiconductor wafer according to claim 1, wherein said plurality of different performances include different etching performances.

5. A semiconductor processing apparatus for processing a semiconductor wafer according to claim 4, wherein the etching performance includes vertical etching or selectivity.

6. A semiconductor processing apparatus according to claim 1, wherein the controller controls one of the plurality of different processing performances, while maintaining the others of the plurality of different processing performances constant.

7. A semiconductor processing apparatus according to claim 1, wherein the controller changes two of the plurality of the different processing performances independently of one another while maintaining the others of the plurality of different processing performances.

8. A semiconductor processing apparatus according to claim 6, wherein the controller controls two input processing parameters so as to control one of the plurality of different processing performances while maintaining the others of the plurality of different performances constant.

9. A semiconductor processing apparatus according to claim 8, wherein the two input processing parameters include flow rate of gases and wafer bias power.