Method and apparatus for local and distributed data memory access (“DMA”) control

• US 7,058,735 B2
• Filed: 06/02/2003
• Issued: 06/06/2006
• Est. Priority Date: 06/02/2003
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Emulex Design & Manufacturing Corp. (Broadcom, Inc.)
• Inventors: Spencer, Thomas Vincent
• Primary Examiner(s): SHIN, CHRISTOPHER B
• Application Number:
  US10/452,330
• Publication Number:
  US 20040243739A1
• Time in Patent Office: 1,100 Days
• Field of Search: 710 5- 6, 710/20, 710/22, 710/69, 710/24, 710 52- 61, 707/10, 707/102, 711/220, 715/863, 712200-245
• US Class Current: 710/24
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

An apparatus for local direct memory access control includes a processor unit for generating a direct memory access designator when needed data is not available and continuing processing which does not require the unavailable data. A memory access designator holder receives the memory access designator, and a local data memory access controller performs a data memory access transaction in accordance with the content of a descriptor. Staging registers hold components of a data memory access designator and transfer the components to a selected portion of the data memory access designator holder. The data memory access controller transfers the contents of the staging registers to the data memory access designator holder when one of the staging registers is written to by the processor unit. The processor unit stalls if a write to the staging register occurs when the data memory access designator holders contain a data memory access designator, and ceases the stall when one of the plurality of data memory access designator holders ceases to contain a data memory access designator.

Claims

1. A processor module having a direct memory access (DMA) control apparatus comprising:

a processor unit for processing data and initiating a generation of one or more local DMA (LDMA) designators upon determining that a portion of the data is unavailable in local memory, and to thereafter continue processing which does not require the unavailable data while waiting for the unavailable data to become available in the local memory;

a LDMA designator holder contained within the processor module and adapted to receive and hold LDMA designator;

a LDMA controller contained within the processor module and communicatively coupled to the LDMA designator holder for receiving the LDMA designator and adapted to carry out a LDMA transaction in accordance with the content of the received LDMA designator to retrieve the unavailable data; and

a plurality of staging registers coupled between the processor unit and the LDMA designator holder, each staging register for storing a different LDMA parameter and for writing a portion of a LDMA designator into a selected portion of the LDMA designator holder;

wherein any one or more of the plurality of staging registers is capable of retaining its stored LDMA parameter between successive writings of LDMA designators to the LDMA designator holder when the LDMA parameter is unchanged so that the one or more staging registers need not be rewritten.

2. The apparatus of claim 1:

wherein the LDMA designator holder is adapted to hold a plurality of LDMA designators, each associated with a LDMA transaction and adapted to present each of the plurality of LDMA designators to the LDMA controller successively.

3. The apparatus of claim 2:

wherein the LDMA designator holder is adapted to store the plurality of LDMA designators in a first-in-first-out configuration.

4. The apparatus of claim 3:

wherein the LDMA controller is adapted to transfer contents of the respective plurality of staging registers to the LDMA designator holder when a selected one of the staging registers is written to by the processor unit.

5. The apparatus of claim 4:

wherein the processor unit is adapted to stall if a write to the selected one of the staging registers occurs when the LDMA designator holder is full and to cease the stall when the LDMA designator holders is not full.

6. A computer and communication link interface comprising the processor module of claim 1.

7. An integrated circuit comprising the processor module of claim 1.

8. A host bus adapter card comprising the processor module of claim 1.

9. A processor module having a direct memory access (DMA) control means comprising:

a processor means for processing data and initiating a generation of one or more local DMA (LDMA) designators upon determining that a portion of the data is unavailable in local memory, and for continuing processing which does not require the unavailable data while waiting for the unavailable data to become available in the local memory;

a LDMA designator holding means contained within the processor means for receiving and holding a LDMA designator;

a LDMA controller means within the processor module and communicatively coupled to the LDMA designator holding means for receiving the LDMA designator and for carrying out a LDMA transaction in accordance with the content of the received LDMA designator to retrieve the unavailable data; and

a plurality of staging means coupled between the processor means and the LDMA designator holding means, each staging means for storing a different LDMA parameter and for writing a portion of a LDMA designator into a selected portion of the LDMA designator holding means;

wherein any one or more of the plurality of staging means is capable of retaining its stored LDMA parameter between successive writings of LDMA designators to the LDMA designator holding means when the LDMA parameter is unchanged so that the one or more staging means need not be rewritten.

10. The apparatus of claim 9:

wherein the LDMA designator holding means includes means for holding a plurality of LDMA designators, each associated with a LDMA transaction and for presenting each of the plurality of LDMA designators to the LDMA controller means successively.

11. The apparatus of claim 10:

wherein the LDMA designator holding means is adapted to store the plurality of LDMA designators in a first-in-first-out configuration.

12. The apparatus of claim 11:

wherein the LDMA controller means includes means for transferring the contents of the respective plurality of staging registers to the LDMA designator holding means when a selected one of the staging register means is written to by the processor means.

13. The apparatus of claim 12:

wherein the processor means including means for stalling if a write to the selected one of the staging register means occurs when the LDMA designator holding means is full and for ceasing the stall when the LDMA designator holding means is not full.

14. A method for providing local direct memory access (DMA) control comprising:

processing data and initiating a generation of one or more local DMA (LDMA) designators upon determining that a portion of the data is unavailable in local memory, and continuing processing which does not require the unavailable data while waiting for the unavailable data to become available in the local memory;

receiving and storing the LDMA designator;

carrying out a LDMA transaction in accordance with the content of the received LDMA designator to retrieve the unavailable data;

forming each LDMA designator from a plurality of staging registers, each staging register storing a different LDMA parameter and writing a portion of a LDMA designator into a selected portion of the LDMA designator holder; and

retaining a value of the LDMA parameter in any one or more of the staging registers between successive writings of LDMA designators when the LDMA parameter is unchanged so the one or more staging registers need not be rewritten.

15. The method of claim 14 further comprising:

receiving and storing a plurality of LDMA designators, each associated with a LDMA transaction, and presenting each of the plurality of LDMA designators successively for carrying out successive LDMA transactions in accordance with the content of the plurality of LDMA designators.

16. The method of claim 15 further comprising:

storing the plurality of LDMA designators in a first-in-first-out configuration.

17. The method of claim 16 further comprising:

transferring the contents of the respective plurality of staging registers to the LDMA designator holder when a selected one of the staging registers is written to.

18. The method of claim 17 further comprising:

stalling the processing of data if a write to the selected one of the staging registers occurs when no more LDMA designators can be stored in the LDMA designator holder, and ceasing the stall when a LDMA designator can once again be stored in the LDMA designator holder.