Bus system and bus interface for connection to a bus

• US 7,058,747 B2
• Filed: 09/24/2002
• Issued: 06/06/2006
• Est. Priority Date: 09/27/2001
• Status: Expired due to Term

• Current Assignee: ST-Ericcson SA (Telefonaktiebolaget LM Ericsson)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Zhang, Zhenyu, Chang, Yeow Khai
• Primary Examiner(s): Perveen, Rehana
• Assistant Examiner(s): VU, TRISHA U
• Application Number:
  US10/253,284
• Publication Number:
  US 20030101308A1
• Time in Patent Office: 1,351 Days
• Field of Search: 710/305, 710 15- 19, 710/46, 710/220, 710/109, 710/110, 710/306, 710/311
• US Class Current: 710/305
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 13/426 using an embedded synchronisation, e.g. Firewire bus, Fibre Channel bus, SSA bus

Abstract

The invention relates to a bus system comprising a first station and a second station coupled by a bus for transferring data and control signals. The bus is conceived to operate according to a protocol in which the first station repeatedly sends requests to the second station. The first station comprises a processor, a bus interface, and a buffer coupled to said interruptible processor and said bus interface, the processor being operable to generate request properties for the requests to be sent by the first station. Furthermore, the processor is operable to handle said data items. The buffer is operable to store said request properties. The bus interface is operable to generate said requests from said stored request properties and to repeatedly send said requests.

Claims

1. A bus system comprising a first station and a second station coupled by a bus for transferring data and control signals, said bus operating according to a protocol in which said first station repeatedly sends requests to said second station characterized in that said first station comprises a processor, a bus interface, and a buffer coupled to said processor and said bus interface, where

said processor is operable to generate request properties for said requests and for handling said data items, wherein the request properties include a polling rate of said requests;

said buffer is operable to store said request properties;

said bus interface is operable to generate said requests from said stored request properties and to repeatedly send said requests, wherein the bus interface adjusts the rate at which the requests are sent as a function of the polling rate included in the request properties.

2. A bus system as claimed in claim 1, characterized in that said request properties also comprise a payload of said requests.

3. A bus system as claimed in claim 1, characterized in that said second station responds to said requests, that said processor is an interruptible processor and that said bus interface is operable for interrupting said processor upon reception of selected responses of said second station.

4. A bus system as claimed in claim 1, characterized in that said bus system is a USB system.

5. A bus interface comprising a connection for a bus and an input for receiving request properties from a processor, characterized in that said bus interface comprises a buffer operable to store said request properties and a controller operable to generate requests out of the stored request properties and to repeatedly send said requests to the connection,

wherein the request properties include a polling rate of said requests, and wherein the bus interface adjusts the rate at which the requests are sent as a function of the polling rate included in the request properties.

6. A bus interface as claimed in claim 5, characterized in that said request properties also comprise a payload of said requests.

7. A bus interface as claimed in claim 7, characterized in that said bus interface also comprises an interrupt output for sending an interrupt signal to an interruptible processor, and that said controller is operable to receive responses from said connection and to interrupt said processor upon reception of selected responses by sending an interrupt signal to the interrupt output.

8. A bus interface as claimed in claim 7, characterized in that said bus interface is operable to operate as a USB interface.