ATA device control via a packet-based interface

• US 7,058,748 B1
• Filed: 06/28/2002
• Issued: 06/06/2006
• Est. Priority Date: 09/27/2000
• Status: Expired due to Term

• Current Assignee: Intellectual Ventures II LLC (Intellectual Ventures LLC)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Castleberry, James E., Jacobs, Daniel G.
• Primary Examiner(s): Auve, Glenn A.
• Assistant Examiner(s): Lee, Christopher E.
• Application Number:
  US10/186,884
• Time in Patent Office: 1,439 Days
• Field of Search: 710/315, 710/35, 710/2, 710/22, 711/219, 711/112, 709/250, 714/724, 714/42, 341/100, 345/11, 702/187
• US Class Current: 710/311
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices

Abstract

ATA devices, such as mass storage units, have increasingly larger storage sizes that use larger configuration register sizes. A command block format allows the USB/ATA bridge circuit to be used with ATA devices with larger registers and at the same time operates with earlier ATA command block formats.

Claims

1. A packet-to-ATA bridge device, comprising:

an interface receiving a packet comprising an Advanced Technology Attachment (ATA) command block for executing ATA register transactions, wherein the command block includes a signature field identifying the command block as an ATA command block and a subcommand field indicating an extended or nonextended register addressing scheme associated with the ATA register; and

an ATA adapter identifying the register addressing scheme according to a predefined value in the subcommand field, addressing an ATA device with the extended or a nonextended register addressing scheme corresponding with the command block extended or nonextended register addressing scheme identifier in the subcommand field, executing either extended or nonextended ATA commands in the command block, and conducting the ATA register transactions in the ATA device addressed according to the identified register addressing scheme.

2. The device according to claim 1 wherein a single command block designates the extended or nonextended register addressing scheme and contains extended or nonextended ATA commands for performing the associated extended or nonextended ATA register transactions.

3. The device according to claim 1 wherein the ATA command block includes a register select field located before an action select field.

4. The device according to claim 1 wherein the ATA command block includes separate most significant and least significant fields for accessing different registers in an ATA device.

5. The device according to claim 4 wherein the ATA command block includes a most significant and least significant sector count field, sector number field, cylinder low field, and cylinder high field.

6. The device according to claim 1 wherein the ATA command block includes multiple bits representing an exponential for a transfer block size value.

7. The device according to claim 1 wherein the ATA adapter writes a device head register using either a value in the ATA command block or an internal value in the bridge device according to a device override flag.

8. The device according to claim 1 wherein the ATA adapter enables a device selection bit in a device selection register to be written to independently from other bits in the device selection register.

9. The device according to claim 1 wherein the interface includes command block wrapper buffer that receives the ATA command block as a USB packet from a host over a Universal Serial Bus and the ATA adapter includes a command block wrapper interpreter determining whether the ATA command block corresponds to ATA register transactions in an ATA device having extended or nonextended register addressing scheme, an ATA protocol state machine parsing the command block into a sequence of ATA register-delivered transactions corresponding to extended or nonextended ATA commands contained in the ATA command block, and an ATA register protocol adapter state machine performing the sequence of ATA register-delivered transactions corresponding to the extended or nonextended ATA commands.

10. A method of operating a packet-to-ATA bridge circuit, comprising:

receiving a packet comprising an ATA command block, wherein the command block includes a signature field identifying the command block as an ATA command block and a subcommand field indicating a register addressing scheme;

executing either extended or nonextended ATA commands in the command block, wherein executing the ATA commands comprises;

identifying the register addressing scheme in the ATA command block according to predefined values in the signature field and the subcommand field;

addressing an ATA device having the extended or nonextended register addressing scheme;

parsing the command block into a sequence of register operations according to the extended or nonextended register addressing scheme; and

sending the sequence of register operations to the ATA device addressed.

11. The method according to claim 10 wherein the same command block designates the register addressing scheme and contains the extended or nonextended ATA commands.

12. The method according to claim 10 including identifying a nonextended addressing scheme associated with the command block and parsing the command block into a sequence of register operations according to the nonextended register addressing scheme.

13. The method according to claim 10 including writing a DEV value into a device head register independently of other values in the device head register.

14. The method according to claim 10 including writing a device head register using a value from the command block or using a value from the bridge circuit.

15. The method according to claim 10 including:

identifying an extended register addressing scheme associated with the command block; and

parsing the command block into a sequence of ATA register operations according to the extended register addressing scheme.

16. The method according to claim 10 including accessing a most significant address value for a register in an Advanced Technology Attachment (ATA) device and accessing a least significant address value for the register in the ATA device.

17. A host, comprising:

a processor generating a command block containing register access information for executing Advanced Technology Attachment (ATA) register-delivered transactions, the command block including fields for a signature field identifying the command block as an ATA command block, a subcommand field indicating a register addressing scheme associated with the ATA register-delivered transactions, a most significant ATA register address field and a least significant ATA register address field, and either extended or nonextended ATA commands, wherein the same command block designates the extended or nonextended register addressing scheme and contains the extended or nonextended ATA commands for performing the associated extended or nonextended ATA register transactions.

18. The host according to claim 17 wherein the register addressing scheme comprises a first ATA addressing scheme and a second ATA addressing scheme according to predefined values in the signature field and the subcommand field.

19. The host according to claim 18 wherein the first ATA addressing scheme is for 28 bit ATA transactions and the second ATA addressing scheme is for 48 bit ATA transactions.

20. The host according to claim 17 including an interface for transferring the command block over a Universal Serial Bus (USB) to a U.S.B-to-ATA bridge.